Patents by Inventor Tamio Nakai

Tamio Nakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Array substrate comprising semiconductor contact layers having same outline as signal lines
    Patent number: 6078366
    Abstract: An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127).
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: June 20, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Hideo Kawano, Akira Kubo, Makoto Shibusawa, Tetsuya Iizuka, Tamio Nakai, Kazushige Mori
  • Array substrate for display device and manufacturing method thereof
    Patent number: 6028652
    Abstract: An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127).
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: February 22, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Hideo Kawano, Akira Kubo, Makoto Shibusawa, Tetsuya Iizuka, Tamio Nakai, Kazushige Mori
  • Array substrate for displaying device with capacitor lines having particular connections
    Patent number: 5966190
    Abstract: An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127).
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: October 12, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Hideo Kawano, Akira Kubo, Makoto Shibusawa, Tetsuya Iizuka, Tamio Nakai, Kazushige Mori
  • Array substrate with bus lines takeout/terminal sections having multiple conductive layers
    Patent number: 5835177
    Abstract: An array substrate includes plural scanning lines (111); a thin film transistor (112) having a first dielectric film (115), (117), a semiconductor film (120) thereon, and a source electrode (126b) electrically coupled to the semiconductor film (120) and a drain electrode (126a); a signal line (110) as taken out of the drain electrode (126a) to extend at substantially right angles to the scanning lines (111); and a pixel electrode (131) electrically connected to the source electrode (126b), wherein the pixel electrode (131) is electrically connected to the source electrode (126b) through a second dielectric film (127) as disposed on at least the signal line (110) while the pixel electrode (131) overlaps an elongate region (113) from its neighboring scanning line (111) through the first and second dielectric films (115), (117), (127).
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: November 10, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohjo, Hideo Kawano, Akira Kubo, Makoto Shibusawa, Tetsuya Iizuka, Tamio Nakai, Kazushige Mori