Abstract: A system and method for reading multi-bit memory cells. The invention resides in employing a plurality of comparators to compare the voltage contained in a multi-bit memory cell with a reference voltage, where each comparator is associated with a single pair of bit lines. For each pair of bit lines, a first bit line is coupled to a multi-bit memory cell and a second bit line is coupled to a dummy cell containing a reference voltage. The first bit line is also coupled to a data bus. The data bus is configured to connect the first bit line to a first input of each of a plurality of comparators that are associated with other bit lines and memory cells. Each comparator has a unique reference voltage applied to its second input. Each comparator compares the voltage on the first bit line with the applied reference voltage and outputs the result of this comparison to a controller.

Abstract: An improved multi-bit memory cell includes a storage capacitor and a switching element coupled to one of the terminals of the capacitor. The switching element includes a first switching component having a positive threshold, and a complementary switching component having a negative threshold. Because the switching element is constructed in this manner, noise generation caused by activation of the switching components is significantly reduced, and cut-off effects are eliminated. Both of these factors contribute to the memory cell's ability to store more bits of information than prior art memory cells.

Abstract: A random access memory, having multi-bit memory cells, includes a successive approximation analog-to-digital (SAAD) converter and a comparator for reading data from the memory cells. In reading data from a cell, the SAAD generates a first reference voltage. This first reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a first comparison result. Based on this first comparison result, a first bit of data is determined. Thereafter, the SAAD generates a second reference voltage based on the first reference voltage and the first comparison result. This second reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a second comparison result. Based on this second comparison result, a second bit of data is determined.

Abstract: A memory has a plurality of memory cells that each store a voltage signal indicative of a multiple bit signal. Each logic value of the multiple bit signal has a unique voltage range. The voltage ranges are unequal and are selected so that the decay of the voltage of the voltage signal in the range remains in the range for each level at a predetermined time. This memory provides logic levels so that the decay time of the voltage signal is greater for larger voltages of the voltage signal. The decay time in each logic level is almost equal. A voltage generator provides the voltage signal to the memory cells responsive to a multiple bit digital data signal. The voltage generator may include a digital-to-analog converter that provides the voltage signal and has at least one more bit than the multiple bit digital data signal. A memory stores a lookup table and provides another multiple bit data signal to the digital-to-analog converter responsive to the multiple bit digital data signal.

Abstract: A coaxial line assembly in a package which houses a high frequency element. The assembly includes a metal wall having a hole extending through the metal wall. The metal wall has a step at substantially an intermediate portion of the hole to define a smaller diameter, inner hole portion opened to the inside of the package and a larger diameter, outer hole portion opened to the outside of the package. A lead for transmitting a high frequency signal passes through the hole and is hermetically sealed in the outer hole portion by glass filled in the outer hole portion. A sealing plate closes an opening of the inner hole portion at the step, the lead extending through the sealing plate. The sealing plate is made of a dielectric material having a dielectric constant near to that of the glass and a melting point higher than that of the glass.

Abstract: A random access memory, having multi-bit memory cells, includes a successive approximation analog-to-digital (SAAD) converter and a comparator for reading data from the memory cells. In reading data from a cell, the SAAD generates a first reference voltage. This first reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a first comparison result. Based on this first comparison result, a first bit of data is determined. Thereafter, the SAAD generates a second reference voltage based on the first reference voltage and the first comparison result. This second reference voltage is compared, by the comparator, to the voltage stored in the cell to derive a second comparison result. Based on this second comparison result, a second bit of data is determined.

Abstract: A semiconductor memory device according to the present invention comprises a number of memory cells that store multiple voltage levels. Each voltage level is uniquely assigned to a different logic level. Multiple binary codes are converted to various analog voltage levels by a digital to analog converter. The memory cell of the invention comprises a storage capacitor and transfer gates, each terminal of which is connected to a bit line through the transfer gate for isolating the storage capacitor from the interference of other circuits while it is not accessed. In the writing cycle, analog voltage can be stored in the storage capacitor of each cell by applying the assigned analog voltage generated by the digital to analog converter through, bit lines and the transfer gates that control the conductivity between the bit lines and storage capacitor.

Abstract: A FM-CW radar device is provided for frequency-modulating a high frequency signal with a modulation signal, transmitting the modulated high frequency signal, receiving a signal reflected by a target object and frequency-modulating the reflection signal with a signal generated by a local oscillator signal source provided by branching a portion of the transmitting signal. A modulator is disposed between a radar transmitting section and a transmitting antenna. The modulator modulates the transmitting signal with a second frequency which is far lower than the radar transmitting frequency and twice as much as the sum or the difference of a Doppler frequency generated by a relative propagation velocity and a beat frequency generated by a propagation delay time. A first frequency converter frequency modulates the received signal reflected by the target object with the local oscillator.

Abstract: A card-type IC-mounting board for detachably setting in a selected type of device, and for controlling predetermined external equipment relating the device. The card-type IC mounting board includes a card-type base plate made of an insulating material of a predetermined size, and an IC-based circuit structure formed on the base plate. The circuit structure includes a microprocessor for execution of predetermined functions to control the external equipment. A first and second discrete region are defined on the base plate, and the circuit structure includes a first circuit section formed on the first region and a second circuit section formed on the second region. The first circuit section includes a microprocessor and an auxiliary circuit, for assisting in the operation of the microprocessor. The second circuit section is for controlling the external equipment in accordance with the microprocessor.

Abstract: An apparatus for assembly and testing of an IC element having a first section designated for primary functions of the IC element and a second section designated for testing of the IC element, including a substrate made of a film of insulating material and having an IC-mounting portion defining a position of IC element to be assembled a plurality of first leads mounted on the substrate and connected to the first section of the IC element when mounted to the IC-mounting portion, a plurality of second leads connected to the second section of the IC element, a single first test pad for connection of the first leads thereto, second test pads for connection of the respective second leads thereto and circuit for connecting the first leads to at least one of the second leads for testing the IC element through the first and second pads.

Abstract: A complete close-contact type image sensor which comes into contact with an original and reads information from the original and which includes a sensor element for photoelectro conversion of a light signal reflected from the original and electronic parts such as a driven unit for driving the sensor element and taking out an electric signal stored in the sensor element, the image sensor being characterized in that the electronic parts such as the driving unit are disposed inside a plane including the surface of contact with the original. According to the above construction of the present invention, since the electronic parts, including the driving unit, are disposed inside the plane which includes the surface of contact with the original, the path of transfer of the original can be made rectilinear to stabilize the feed of the original without enlarging the gap between the sensor element and the original.

Abstract: A liquid crystal display apparatus comprising a liquid crystal display panel, plate-like light introducing means disposed behind the liquid crystal display panel, at least one light source receiving portion formed in the intermediate portion of the light introducing means, a light source disposed in the light source receiving portion, light diffusing means disposed between the light source and the liquid crystal display panel in front of at least the light source receiving portion, and light reflecting means disposed behind the light source.

Abstract: A memory device for use with an external apparatus having a predetermined function is removably attached to the apparatus and comprises a connection portion for electrically removably connecting the memory device to the external apparatus; a memory portion for storing information supplied from the external apparatus through the connection portion so as to be accessible from the external apparatus, the memory portion being of a type which requires periodical refreshing of the stored information; a reproducing and holding circuit actuated in response to at least one predetermined signal supplied from the external apparatus through the connection portion to refresh the information stored in the memory portion; and an actuating circuit for actuating operation of the reproducing and holding circuit when the connection portion is electrically separated from the external apparatus, the actuating circuit including a power source for electrically energizing the reproducing and holding circuit and a signal generation c

Abstract: Plural semiconductor elements are buried into an insulating substrate, and top surfaces of semiconductor elements and the substrate are in a same plane. A photosensitive dry film is covered on surfaces of the substrate and semiconductor elements. The photosensitive dry film has openings corresponding to electrodes of semiconductor elements, and conductors are filled in openings of the photosensitive dry film. The device has the multi-layer wiring construction without damaging to semiconductor elements arranged on the substrate.

Abstract: An IC chip is packaged on a film carrier. The film carrier comprises an insulation film and many conductive leads formed on the insulation film in predetermined patterns. Each of the leads has an inner lead portion to be connected to a terminal of the IC chip, and an outer lead portion to be connected to a conductive pattern of a mounting board. The film carrier further comprises an embankment, which is made of insulation material and formed on and/or in the vicinity of the outer lead portions of the leads to prevent an ooze of resin when the IC chip is sealed with the resin.

Abstract: A semiconductor integrated circuit device according to the present invention comprises a chip substrate formed of a semiconductor. Formed on a surface of the chip substrate is an integrated circuit and a plurality of chip terminals which are located to the outside of the integrated circuit, so as to be connected thereto. An electrical insulating layer covers the entire surface of the chip substrate, and conductor leads equal in number to the chip terminals are formed on the insulating layer. One end of each conductor lead is connected to a corresponding chip terminal, and the other end thereof is formed having a connecting terminal whose surface area is greater than that of each chip terminal. The connecting terminals are distributed substantially over the entire surface of the insulating layer.

Abstract: An image sensor having first wires formed in parallel on a first region of a substrate; a semiconductor layer formed on the first region covering the first wires and on a second region of said substrate; first electrodes arranged in line, connecting to the semiconductor layer of said second region; second electrodes arranged in line and connected to the semiconductor layer of said second region, and second wires extended from the first electrodes, the second wires connecting the first electrodes to said first wires at through holes formed in said semiconductor layer. The second electrodes are formed as a common electrode, and each of the first electrode, together with a portion of the second electrode facing the first electrodes and the semiconductor layer forming a photo-sensing element.

Abstract: An image sensor, comprising a semiconductor layer formed on at least a first region of a substrate; first electrodes arranged in line and electrically connected to the semiconductor layer of said first region; and second electrodes arranged in line and electrically connected to said semiconductor layer of said first region. The second electrodes are respectively formed as a common electrode, and each of the first electrodes, a portion of said second electrode facing the first electrode and the semiconductor layer positioned therebetween form a photo-sensing element. First wires respectively extend from said first electrodes to a second region of said substrate. An insulating layer is continuously formed on the first and second regions, covering said photo-sensing elements and the first wires as well as second wires formed in parallel on the insulating layer of said second region. The second wires are electrically connected to the first wires at through holes formed in the insulating layer.

Abstract: A microchannel plate has a platelike photosensitive glass substrate and a plurality of microchannels formed separately from each other and extending across the thickness of the substrate. A secondary electron-emission surface is formed on an inner surface of each of the microchannels. Accelerating electrodes formed on two opposite sides of the photosensitive glass substrate, so as to be partially in electrical contact with the secondary-emission surface. The microchannels are formed by applying ultraviolet rays to the substrate through a mask and removing irradiated portions of the substrate by etching.

Abstract: A contact-type linear image sensor has two separate substrates aligned adjacent to each other. A linear array of amorphous silicon photoelectric converting elements serving as photoelectric cells and a matrix wiring unit are provided on a first substrate. Driver IC chips are mounted on a second substrate. Connection pad patterns for common cell electrodes of cell groups and connection pad patterns for row signal lines of the matrix wiring unit are provided concentrically at a peripheral edge of the first substrate to be aligned along a junction edge line defined between the substrates. Connection pad patterns for the IC chips are linearly aligned at a peripheral edge of the second substrate and along the substrate junction edge line to oppose the pad patterns of the first substrate. A connector unit for electrically connecting the pad patterns of the first and second substrates may be provided at only one position of the junction edge portion of the first and second substrates.