Abstract: A voltage stabilizing circuit is provided between an insulated converter and a non-insulated converter. When an input voltage Vin from the insulated converter rises, a base current Ib is caused to flow into a transistor via a capacitor, thereby causing a collector current Ic that is hfe times larger than the base current Ib to flow into a collector of the transistor. As a result, a capacitance C of the capacitor is caused to produce approximately the same effect as that produced in a case where a capacitor whose capacitance is equivalent to a value obtained by multiplying the capacitance by the current amplification factor hfe of the transistor is inserted between a power supply line and a ground.

Abstract: A tertiary coil is provided in a DC/DC converter. An electric current is generated in the tertiary coil due to on an alternating-current voltage produced in the tertiary coil. An electrical current supplying circuit supplies the electric current generated in the tertiary coil to a load when supplementary power must be supplied to the load.

Abstract: A semiconductor dynamic random access memory device has shared sense amplifier units used for not only magnification of data bits but also serving as a cache storage, and a cache system incorporated in the semiconductor dynamic random access memory device individually controls the sense amplifier units to determine whether to allow an access to the selected sense amplifier unit, thereby enhancing the hit ratio.

Abstract: A DRAM using a divided word line scheme has a cache operation capability. A cache line has a data corresponding to sub-block data. Each data set of sub-block is related to the individual main word address. The DRAM has an extra data storage for selecting a data transfer mode between a sense latch and the storage. With the storage, the DRAM is capable of transferring a plurality of data sets having different row addresses to the sense latch at the same time.

Abstract: A memory access request signal is generated with activation of three different signals, i.e., memory select signal, operating mode signal and operating input signal. When only the memory select signal and operating mode signal are activated, internal operation is not executed, and only an operating mode for determining access allow signal generation timing is determined. The access allow signal is generated at the same timing as the execution of the operating mode.

Abstract: A dynamic semiconductor memory device includes a timing signal generator for controlling a precharge operation such that the predetermined precharge operation is completed, during a memory refresh cycle, for a sense amplifier and bit lines corresponding thereto for the next memory access. The memory device using the sense amplifier as cache keeping means is capable of increasing the memory access speed immediately after a memory refresh operation.

Abstract: In a dynamic DRAM device including a plurality of memory cell blocks associated with sense amplifier arrays as cache memories, and registers for storing addresses of the memory cell blocks to indicate the contents of the sense amplifiers, a refresh address for a self-refresh mode is sequentially generated to perform a refresh operation upon the memoty cell blocks. When the refresh address coincides with a predetermined value, data of the memory cell blocks is read by using an address of one of the registers and is restored in a corresponding sense amplifer array.

Abstract: Louver segments of a heat transfer fin each have a longitudinal central portion disposed at the center of the louver segment in a direction crossing the flow of a fluid and longitudinal end portions each disposed on either side of the longitudinal central portion and sectioned into parts. Each louver segment has a configuration such that an area of the longitudinal central portion projected in the direction of the flow of the fluid is larger than an area of each of the longitudinal end portions projected in the direction of the flow of the fluid, with respect to the same width of the passage of the fluid.

Abstract: A random access memory device has memory cell blocks, row address decoders respectively associated with the memory cell blocks, sense amplifier circuit arrays each shared between two of the memory cell blocks, and a column selecting unit for transferring a data bit from one of the sense amplifier circuit arrays to an output data buffer circuit, a flag generating unit for producing flag signals indicative of memory cell blocks supplying the data bits presently stored in the sense amplifier circuit arrays, and an address discriminating unit operative to examine block and row addresses supplied from the outside thereof to see whether or not an accessed data bit has been already stored in the sense amplifier circuit arrays, thereby allowing the shared sense amplifier circuit arrays to serve as a cache memory.

Abstract: Fans are disposed on an upper wall face out of the upper wall face, a lower wall face and side wall faces which constitute an outside frame of a machine body. An air-cooled absorber is disposed on two adjacent wall faces. An air-cooled condenser is disposed on one wall face of the remaining side wall faces. A main apparatus comprising such as an evaporator, a high-temperature regenerator, a low-temperature regenerator, a solution heat exchanger and pipes for connecting operatively the apparatuses together is disposed on an inner portion of the machine body so as to be surrounded by the air-cooled absorber and the air-cooled condenser. Thus, a noise generated from the refrigerating machine is reduced.