Abstract: An electronic circuit for Random Number Generation (RNG) includes multiple inverters, a contention-current generator, and digitization circuitry. The multiple inverters are connected to one another in a ring and configured to generate an oscillating signal. The contention-current generator is connected to a node at which an output of an inverter of the ring drives an input of a subsequent inverter of the ring with a drive current. The contention-current generator includes at least a buffer configured to drive the node, at least while a voltage at the node transitions between opposite logic states, with a contention current that opposes the drive current and is weaker than the drive current. The digitization circuitry is configured to generate a sequence of random numbers by sampling the oscillating signal generated in the ring.

Abstract: An integrated circuit includes signal-source circuitry (SSC), an SSC power supply circuit (SSC-PS) and a digitization circuit. The SSC is configured to generate an output signal, which is guaranteed to meet specified electrical parameters provided that a supply voltage to the SSC is within a specified operating voltage range. The SSC-PS is configured to power the SSC with a reduced voltage that is below the specified operating voltage range, thereby causing the output signal to be noisy. The digitization circuit is configured to digitize the noisy output signal so as to generate a respective sequence of random numbers.

Abstract: A secure Integrated Circuit (IC) includes functional circuitry, and protection circuitry configured to protect the functional circuitry against fault-injection attacks. The protection circuitry includes a plurality of digital detection cells, and protection logic. The detection cells have respective inputs and outputs and are connected output-to-input in at least a chain. In response to a fault-injection attack, a given detection cell in the chain is configured to toggle an output that drives an input of a subsequent detection cell in the chain, thereby causing a pulse to propagate along the chain. The protection logic is configured to receive the pulse from the chain and initiate a responsive action.

Abstract: A Random-Number Generator (RNG) includes a first plurality of High-Frequency (HF) clock generators, a second plurality of Low-Frequency (LF) clock generators, a third plurality of Digital Random-Number Generator circuits (DRNGs), and a multiplexer. The HF clock generators are configured to generate respective HF clock signals in a first frequency range. The LF clock generators are configured to generate respective LF clock signals in a second frequency range, lower than the first frequency range. Each DRNG is configured to derive a respective random-bit sequence from (i) a respective HF clock signal taken from among the HF clock signals and (ii) a respective LF clock signal taken from among the HF clock signals. The multiplexer is configured to produce an output sequence of random bits from random-bit sequences generated by the DRNGs.

Abstract: A secure Integrated Circuit (IC) includes functional circuitry, and protection circuitry configured to protect the functional circuitry against fault-injection attacks. The protection circuitry includes a plurality of digital detection cells, and protection logic. The detection cells have respective inputs and outputs and are connected output-to-input in at least a chain. In response to a fault-injection attack, a given detection cell in the chain is configured to toggle an output that drives an input of a subsequent detection cell in the chain, thereby causing a pulse to propagate along the chain. The protection logic is configured to receive the pulse from the chain and initiate a responsive action.

Abstract: An electronic circuit includes a native N-channel Metal-Oxide-Semiconductor (NMOS) transistor and a P-channel Metal-Oxide-Semiconductor (PMOS) transistor. The gates of the native NMOS transistor and the PMOS transistor and the source of the native NMOS transistor are grounded. The drains of the native NMOS transistor and the PMOS transistors are connected to one another and to an output port, and the source of the PMOS transistor is connected to an input voltage.

Abstract: Apparatus includes a single-pin input interface, which is operative to sense a voltage across a capacitor of a Resistor-Capacitor (RC) network in which the capacitor is repetitively charging and discharging so that the voltage oscillates as a function of time. A measurement circuit is coupled to measure time durations in which the capacitor is charging and in which the sensed voltage lies between first and second predefined thresholds. A clock generation circuit is coupled to generate an output clock signal having a frequency, and to adjust the frequency responsively to the measured time durations.

Abstract: Apparatus includes a single-pin input interface, which is operative to sense a voltage across a capacitor of a Resistor-Capacitor (RC) network in which the capacitor is repetitively charging and discharging so that the voltage oscillates as a function of time. A measurement circuit is coupled to measure time durations in which the capacitor is charging and in which the sensed voltage lies between first and second predefined thresholds. A clock generation circuit is coupled to generate an output clock signal having a frequency, and to adjust the frequency responsively to the measured time durations.