Abstract: An intelligent controllability check process can intelligently examine if enumeration of some possible values for a set of control signal inputs can be avoided (e.g., resulting in less than all possible values being enumerated, etc.). A modified intelligent QBF controllability check can be utilized, including a modified intelligent QBF solver. The process can include a formal controllability check with an extensive or exhaustive consideration of possible value assignments while avoiding enumeration of some possibilities. The formal controllability check can examine if a proof establishes a conclusion regarding assignment values. The proof can be utilized in determining possible results including: (1) a conclusion that signals provide controllability; (2) a conclusion that signals do not provide controllability; or (3) can not reach a conclusion one way or other if signals do or do not provide controllability. Results (e.g., SAT, UNSAT, etc.) of the QBF controllability check can be verified.

Abstract: A method of generating a digital circuit model that has fewer latches than the circuit being modeled. Initially, a determination of whether the digital circuit is reducible is made. The digital circuit suitably includes one or more primary inputs, one or more primary outputs, and a plurality of latches comprised of a level one (L1) latch set and a level two (L2) latch set wherein the latch sets may or may not lack one-to-one correspondence. After determining that the digital circuit is reducible, at least one of the latches is replaced with combinational logic thereby reducing the latch count of the digital circuit model.