Patents by Inventor Tamiya Onodera
Tamiya Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080104595Abstract: A system of the present invention includes: a memory device which includes a first memory area for storing first information indicating that a first task acquires or attempts to acquire a lock, and a second memory area for storing second information indicating that a second task acquires or attempts to acquire the lock, and in which a time lag may occur between a time when the first task issues a writing instruction and a time when the written content is enabled to be referred to by the second task; a first acquisition section which reads the second memory area after issuing a writing instruction to write the first information to the first memory area in response to a request from the first task, and which makes a reply indicating a success of the lock acquisition on condition that the second information is not read; and a second acquisition section which writes the second information to the second memory area in response to a request from the second task, which enables the written content to be referred to bType: ApplicationFiled: October 17, 2007Publication date: May 1, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kiyokuni Kawachiya, Akira Koseki, Tamiya Onodera, Graeme Johnson
-
Patent number: 7337298Abstract: Memory segments are allocated for a classloader to store class information, such as by selecting an allocation approach based on classloader type. In a first approach, in response to each request, a segment having a fixed size is allocated. In a second approach, in response to a first request, a first segment having a size equal to an amount of memory needed to store information related to the request is allocated. In response to a second request, a second segment having a second size is allocated, and in response to a third request, a third segment having a third size greater than the second size is allocated. In a third approach, in response to the first request, a first segment having a first size is allocated. In response to a second request, a second segment having a second size greater than the first size is allocated.Type: GrantFiled: October 5, 2005Date of Patent: February 26, 2008Assignee: International Business Machines CorporationInventors: Kiyokuni Kawachiya, Kazunori Ogata, Tamiya Onodera, Trent A. Gray-Donald
-
Publication number: 20070143381Abstract: A string handling method, program, and information processing apparatus capable of reducing the amount of data stored in a storage. An information processing apparatus handles strings. The information processing apparatus includes a storage storing a group of strings including a plurality of strings each of which consists of a plurality of pieces of character data, a reference section which refers to a particular string in the group of strings, a character data detecting section which detects character data that is not referenced as the particular string in the group of strings, and a character data deleting section which deletes the detected character data from the group of strings.Type: ApplicationFiled: December 8, 2006Publication date: June 21, 2007Inventors: Kiyokuni Kawachiya, Kazunori Ogata, Tamiya Onodera
-
Publication number: 20070078916Abstract: Memory segments are allocated for a classloader to store class information, such as by selecting an allocation approach based on classloader type. In a first approach, in response to each request, a segment having a fixed size is allocated. In a second approach, in response to a first request, a first segment having a size equal to an amount of memory needed to store information related to the request is allocated. In response to a second request, a second segment having a second size is allocated, and in response to a third request, a third segment having a third size greater than the second size is allocated. In a third approach, in response to the first request, a first segment having a first size is allocated. In response to a second request, a second segment having a second size greater than the first size is allocated.Type: ApplicationFiled: October 5, 2005Publication date: April 5, 2007Inventors: Kiyokuni Kawachiya, Kazunori Ogata, Tamiya Onodera, Trent Gray-Donald
-
Publication number: 20060179428Abstract: A method and system are provided for starting a new JAVA application while eliminating overhead associated therewith. The new JAVA application is created from a memory image of an initialized JAVA application. The memory image of the process which is executing the initialized JAVA application is copied to enable the memory image to be observed by the new JAVA application. In addition, to copying the memory image, the states of system resources and operating system monitors not present in the copied memory image are recreated on the JAVA application.Type: ApplicationFiled: February 10, 2005Publication date: August 10, 2006Inventors: Kiyokuni Kawachiya, Tamiya Onodera, Kazunori Ogata, Hideaki Komatsu
-
Publication number: 20060090168Abstract: In a multiprocessor computer system, a lock operation is maintained with a thread using non-atomic instructions. Identifiers are assigned to each thread. Flags in conjunction with the thread identifiers are used to determine the continuity of the lock with a thread. However, in the event continuity of the lock with the thread ceases, a compare-and-swap operation is executed to reset the lock with the same thread or another thread. Similarly, in the event there has been a collision between two or more threads requesting the lock, a compare-and-swap operation is executed to assign the lock to one of the requesting threads. Accordingly, prolonged ownership of a lock operation by a thread is encouraged to mitigate use of atomic operations in granting of the lock to a non-owning thread.Type: ApplicationFiled: September 28, 2004Publication date: April 27, 2006Inventors: Takeshi Ogasawara, Akira Koseki, Hideaki Komatsu, Kiyokuni Kawachiya, Tamiya Onodera
-
Patent number: 6971102Abstract: The present invention provides a technique for skipping a locking process for an object in memory when a thread accesses an object that only it will access in order to reduce the load imposed on a system and to improve the overall system performance. A program executing in a computer system has multiple threads that share and access objects stored in memory. The objects have thread locality flags associated therewith that indicate the presence or absence of thread localities. The threads examine the thread locality flags for the objects they attempt to access to determine whether the corresponding objects, which are to be accessed, have localities for the threads. If, so the, threads skip the locking process and access objects immediately. If not, the object is locked prior to being accessed.Type: GrantFiled: March 9, 2001Date of Patent: November 29, 2005Assignee: International Business Machines CorporationInventors: Kiyokuni Kawachiya, Tamiya Onodera
-
Publication number: 20050177821Abstract: The same executable instruction stream as an executable instruction stream generated by a dynamic compiler is reproduced to facilitate debugging of the dynamic compiler. Provides compiler program for computer functioning as: an execution status obtaining section for obtaining an execution status of the program; a dynamic compilation section for compiling one of the partial programs to be executed during execution of the program; an execution status recording section for recording the execution status in a memory area allocated on a memory of the computer; a file reading section for reading a file containing contents of the memory area allocated on the memory; and a replay compilation section for compiling the one partial program on the basis of the execution status obtained from the file to generate the same executable instruction stream as the executable instruction stream generated by the dynamic compilation section during the execution of the program.Type: ApplicationFiled: January 25, 2005Publication date: August 11, 2005Applicant: International Business Machines CorporationInventors: Kazunori Ogata, Tamiya Onodera, Hideaki Komatsu
-
Publication number: 20050108697Abstract: Compiler device for optimizing program which manipulates a character string includes append instruction detection unit, store code generation unit, and append code generation unit. The append instruction detection unit detects an append instruction which appends a character string to a string variable for storing a character string, in the program. The store code generation unit generates, a substitute for each of a plurality of the append instructions detected by the append instruction detection unit, a store code for storing data of an appendant character string to be appended to the string variable by the append instruction into a buffer. The append instructions append the character strings to the same string variable. The append code generation unit generates append code for appending a plurality of the appendant character strings to the string variable, at a position executed before an instruction to refer to the string variable in the program.Type: ApplicationFiled: February 25, 2004Publication date: May 19, 2005Applicant: International Business Machines CorporationInventors: Takeshi Ogasawara, Tamiya Onodera, Mikio Takeuchi
-
Patent number: 6886159Abstract: The invention provides a representation method for an object that is fast and has an extremely little effect on the execution efficiency of a processing system. A computer system that implements an object-oriented programming language according to the invention as runtime representation for an object in programming language that is implemented, comprises an object, a type information block, and a class structure, wherein the object has a header including a pointer to the type information block, wherein the type information block has a class pointer pointing to the class structure, wherein a plurality of class pointers are provided depending on the number of states of the object and individual class pointers are associated with individual states of the object, and wherein the pointer included in the header of the object uses lower bits to point to the class pointers individually in order to represent the states of the object.Type: GrantFiled: March 16, 2001Date of Patent: April 26, 2005Assignee: International Business Machines CorporationInventor: Tamiya Onodera
-
Patent number: 6883026Abstract: A hybrid locking method for preventing a reduction in the processing speed of a frequently executed path which includes locking, accessing and unlocking an object is provided. According to the present invention, at least one contention bit is introduced. The contention bit, which is prepared separately from a lock field, is set when a contention occurs in a light-weight lock, and is cleared when a light-weight lock is shifted to a heavy-weight lock (“inflate” function).Type: GrantFiled: August 20, 1999Date of Patent: April 19, 2005Assignee: International Business Machines CorporationInventors: Tamiya Onodera, Kiyokuni Kawachiya
-
Publication number: 20040205701Abstract: The invention provides a representation method for an object that is fast and has an extremely little effect on the execution efficiency of a processing system. A computer system that implements an object-oriented programming language according to the invention as runtime representation for an object in programming language that is implemented, comprises an object, a type information block, and a class structure, wherein the object has a header including a pointer to the type information block, wherein the type information block has a class pointer pointing to the class structure, wherein a plurality of class pointers are provided depending on the number of states of the object and individual class pointers are associated with individual states of the object, and wherein the pointer included in the header of the object uses lower bits to point to the class pointers individually in order to represent the states of the object.Type: ApplicationFiled: March 16, 2001Publication date: October 14, 2004Applicant: International Business Machines CorporationInventor: Tamiya Onodera
-
Publication number: 20040139093Abstract: An exclusion controller which allows an information processing unit to acquire a contended resource to the exclusion of the other information processing units includes a plurality of non-prioritized information processing units mutually exclusively acquiring a non-prioritized exclusion right, which indicates a candidate for acquiring the contended resource, by a first process. The exclusion controller further includes a prioritized information processing unit acquiring the contended resource by a second process, which requires a shorter processing time than the first process, to the exclusion of the non-prioritized information processing unit having acquired the non-prioritized exclusion right.Type: ApplicationFiled: October 23, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: Kiyokuni Kawachiya, Akira Koseki, Tamiya Onodera
-
Publication number: 20010025295Abstract: The present invention provides a technique for skipping a locking process for an object in memory when a thread accesses an object that only it will access in order to reduce the load imposed on a system and to improve the overall system performance. A program executing in a computer system has multiple threads that share and access objects stored in memory. The objects have thread locality flags associated therewith that indicate the presence or absence of thread localities. The threads examine the thread locality flags for the objects they attempt to access to determine whether the corresponding objects, which are to be accessed, have localities for the threads. If, so the, threads skip the locking process and access objects immediately. If not, the object is locked prior to being accessed.Type: ApplicationFiled: March 9, 2001Publication date: September 27, 2001Applicant: International Business Machines CorporationInventors: Kiyokuni Kawachiya, Tamiya Onodera
-
Publication number: 20010014905Abstract: An innovative compound lock method is provided that does not reduce the processing speed attained along a frequent path. When no thread is locking an object (1), a value of 0 is stored both in a lock field and in a contention bit. Then, when a specific thread locks an object (light lock), the identifier of the thread is stored in the lock field (2). If any other thread attempts to acquire a lock before the thread designated by the thread identifier unlocks the object, SPECIAL is stored in the lock field (5), and the process is returned to (1). If a different thread attempts to acquire a lock before the designated thread unlocks the object, this causes a contention to occur in the light lock mode, and a contention bit is set to record it (3). Thereafter, when the lock mode is shifted to the fat lock mode, the contention bit is cleared (4), and if possible, the process is shifted from (4) to (1).Type: ApplicationFiled: December 15, 2000Publication date: August 16, 2001Inventor: Tamiya Onodera
-
Patent number: 5987529Abstract: Message sending can be performed quickly making efficient use of memory space. A class object C is obtained (110) from a specified receiver object. The class object C contains an instance variable pointing to a dispatch table for the class to obtain (120) a dispatch table D. From the code which is an argument of a vmicall instruction, a method M of the address stored in the entry of the code in the dispatch table is retrieved (130). The card which is the other argument of the vmicall instruction is compared (140) with the card number stored in the method M retrieved in step 130. If the card and the card number are not identical, the selector mismatch handler is invoked to locate the correct method to be invoked (150). Then, the method M is invoked (160). In the selector mismatch handler, it is determined whether the dispatch table D for the class C is the default one, and if it is the default dispatch table, the dispatch table for the class C is allocated.Type: GrantFiled: April 4, 1997Date of Patent: November 16, 1999Assignee: International Business Machines CorporationInventors: Hiroaki Nakamura, Tamiya Onodera
-
Patent number: 5898875Abstract: An objects loading method comprising the steps of (1) determining whether an object which is going to be loaded is a first object which is accessed only by another object, (2) if the object which is going to be loaded is determined to be the first object, removing the first object and also at least one second object which is accessed by the first object from the objects to be loaded, and (3) updating a list for managing the loaded objects.Type: GrantFiled: June 19, 1996Date of Patent: April 27, 1999Assignee: International Business Machines Corp.Inventors: Hiroaki Nakamura, Tamiya Onodera, Mikio Takauchi
-
Patent number: 5745749Abstract: To improve the efficiency in space of per-file clustering. According to the multiple version clustering of this invention, the difference which occurred from modification to the program information of a single source file is initially added to the same cluster as the one holding, the program information of the original source file. This is similar to per-file clustering. What is different from per-file clustering is that each time a difference is added, the amount of the difference is determined by units of byte, for example. Then, in accordance with the invention, in response to the occurrence of the amount of difference accumulation exceeding a predetermined amount, another cluster is created. At this time, the separate cluster will not accommodate another difference, but the entire program information of the modified source file. Differences brought by further modifications are accumulated not in the old cluster, but in the new cluster.Type: GrantFiled: June 21, 1995Date of Patent: April 28, 1998Assignee: International Business Machines Corp.Inventor: Tamiya Onodera
-
Patent number: 5560015Abstract: A method and program for compiling a source program composed by using one or more program modules. Each program module consists of a first part which defines specifications and a second part which performs functions. The compilation method comprises the steps of:(1) detecting an encounter with a stage using a program module while a source program is analyzed by a compiler object;(2) interrupting the compiler object in operation in response to said detection;(3) searching automatically for said first part of said program module in response to said detection;(4) compiling said first part of said program module thus searched out automatically by a new compiler object; and(5) resuming said compilation by said interrupted compiler object after compilation of said first part of said program module.Type: GrantFiled: May 30, 1995Date of Patent: September 24, 1996Assignee: International Business Machines CorporationInventor: Tamiya Onodera