Patents by Inventor Tamiyu Kato
Tamiyu Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10102915Abstract: The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target.Type: GrantFiled: November 2, 2017Date of Patent: October 16, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tamiyu Kato, Takanobu Suzuki
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Publication number: 20180053557Abstract: The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target.Type: ApplicationFiled: November 2, 2017Publication date: February 22, 2018Inventors: Tamiyu KATO, Takanobu SUZUKI
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Patent number: 9824766Abstract: The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target.Type: GrantFiled: September 2, 2015Date of Patent: November 21, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tamiyu Kato, Takanobu Suzuki
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Patent number: 9570188Abstract: The trimming range of a reference current is extended larger than that of the related art. A semiconductor device includes a reference current generating circuit that generates a reference current. The reference current includes a first base current, a second base current base current, a second base current, a temperature compensating current, and a voltage compensating current. The first base current can be trimmed. The second base current flowing opposite to the first base current can be trimmed. The temperature compensating current flows in the same direction as the first base current and has higher temperature dependence than the first and second base currents. The voltage compensating current flows in the same direction as the first base current and depends on power supply voltages more than the base currents.Type: GrantFiled: February 4, 2016Date of Patent: February 14, 2017Assignee: Renesas Electronics CorporationInventors: Akihiko Kanda, Tamiyu Kato
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Patent number: 9496044Abstract: A memory array (101) includes a plurality of twin cells (104), each of which is composed of a first memory element (102) and a second memory element (103) which are each electrically rewritable and configured to memorize binary data according to a difference in threshold voltages therebetween. A power supply control circuit (105), upon receiving a request for erasing data in a twin cell, increases both the threshold voltage of the first memory element (102) and the threshold voltage of the second memory element (103) during the pre-writing, and after the pre-writing, differentiates the voltage of a first bit line (BL) which is connected to the first memory element (102) and the voltage of a second bit line (/BL) which is connected to the second memory element (103) during the application of erase pulse.Type: GrantFiled: August 15, 2013Date of Patent: November 15, 2016Assignee: Renesas Electronics CorporationInventor: Tamiyu Kato
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Publication number: 20160276038Abstract: The trimming range of a reference current is extended larger than that of the related art. A semiconductor device includes a reference current generating circuit that generates a reference current. The reference current includes a first base current, a second base current base current, a second base current, a temperature compensating current, and a voltage compensating current. The first base current can be trimmed. The second base current flowing opposite to the first base current can be trimmed. The temperature compensating current flows in the same direction as the first base current and has higher temperature dependence than the first and second base currents. The voltage compensating current flows in the same direction as the first base current and depends on power supply voltages more than the base currents.Type: ApplicationFiled: February 4, 2016Publication date: September 22, 2016Applicant: Renesas Electronics CorporationInventors: Akihiko KANDA, Tamiyu KATO
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Patent number: 9436598Abstract: In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.Type: GrantFiled: March 4, 2011Date of Patent: September 6, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tamaki Tsuruda, Tamiyu Kato
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Publication number: 20160180941Abstract: A memory array (101) includes a plurality of twin cells (104), each of which is composed of a first memory element (102) and a second memory element (103) which are each electrically rewritable and configured to memorize binary data according to a difference in threshold voltages therebetween. A power supply control circuit (105), upon receiving a request for erasing data in a twin cell, increases both the threshold voltage of the first memory element (102) and the threshold voltage of the second memory element (103) during the pre-writing, and after the pre-writing, differentiates the voltage of a first bit line (BL) which is connected to the first memory element (102) and the voltage of a second bit line (/BL) which is connected to the second memory element (103) during the application of erase pulse.Type: ApplicationFiled: August 15, 2013Publication date: June 23, 2016Applicant: Renesas Electronics CorporationInventor: Tamiyu KATO
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Publication number: 20160064095Abstract: The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target.Type: ApplicationFiled: September 2, 2015Publication date: March 3, 2016Inventors: Tamiyu KATO, Takanobu SUZUKI
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Publication number: 20150301935Abstract: A program counter (12) updates an address by adding a first value or a second value. A code select circuit (14) selects, in accordance with the address of the program counter (12), one of an insert code retained in an insert code register set block (17) and corresponding to the address specified by the program counter (12), and an original code stored in a flash control code ROM (13) and having the address specified by the program counter (12). An instruction execution unit (15) executes the selected code. At least one of a plurality of original codes and the insert code is a multicycle instruction. The program counter (14) stops update of the address when the multicycle instruction is executed.Type: ApplicationFiled: March 2, 2012Publication date: October 22, 2015Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tamiyu KATO, Yukiko MARUYAMA, Shinya IZUMI, Kiyoshi NAKAKIMURA, Yoshihiro SEGUCHI
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Publication number: 20130339590Abstract: In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.Type: ApplicationFiled: March 4, 2011Publication date: December 19, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tamaki Tsuruda, Tamiyu Kato
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Patent number: 8477535Abstract: A semiconductor device is provided which comprises a nonvolatile memory capable of storing complementary data and performing a more accurate blank check than ever before. A nonvolatile memory comprises a memory array having a plurality of twin cells arranged therein for storing complementary data, and first to third determination units. The first determination unit determines, for each of the twin cells selected by a selection circuit, whether or not a first condition that the threshold voltage of one memory cell is higher than a reference value commonly set and the threshold voltage of the other memory cell is lower than the reference value is satisfied. The second determination unit determines whether or not a second condition that all the selected twin cells satisfy the first condition is satisfied. The third determination unit determines, based on the determination result of the second determination unit, whether or not each of the selected twin cells is in a blank state.Type: GrantFiled: July 11, 2011Date of Patent: July 2, 2013Assignee: Renesas Electronics CorporationInventor: Tamiyu Kato
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Publication number: 20120033495Abstract: A semiconductor device is provided which comprises a nonvolatile memory capable of storing complementary data and performing a more accurate blank check than ever before. A nonvolatile memory comprises a memory array having a plurality of twin cells arranged therein for storing complementary data, and first to third determination units. The first determination unit determines, for each of the twin cells selected by a selection circuit, whether or not a first condition that the threshold voltage of one memory cell is higher than a reference value commonly set and the threshold voltage of the other memory cell is lower than the reference value is satisfied. The second determination unit determines whether or not a second condition that all the selected twin cells satisfy the first condition is satisfied. The third determination unit determines, based on the determination result of the second determination unit, whether or not each of the selected twin cells is in a blank state.Type: ApplicationFiled: July 11, 2011Publication date: February 9, 2012Inventor: Tamiyu KATO
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Patent number: 6515900Abstract: A non-volatile semiconductor memory device includes a bank pointer, in which a signal for designating an operating mode to be performed is generated according to coincidence/non-coincidence of prescribed bits of address signals supplied from an address buffer, and the generated signal is supplied to an internal control circuit. Thus, necessary data can be read out from the non-volatile semiconductor memory device at high speed, so that usability of the device is improved.Type: GrantFiled: April 12, 2001Date of Patent: February 4, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tamiyu Kato, Tomoshi Futatsuya, Yoshikazu Miyawaki
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Publication number: 20010050860Abstract: A non-volatile semiconductor memory device includes a bank pointer, in which a signal for designating an operating mode to be performed is generated according to coincidence/non-coincidence of prescribed bits of address signals supplied from an address buffer, and the generated signal is supplied to an internal control circuit. Thus, necessary data can be read out from the non-volatile semiconductor memory device at high speed, so that usability of the device is improved.Type: ApplicationFiled: April 12, 2001Publication date: December 13, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tamiyu Kato, Tomoshi Futatsuya, Yoshikazu Miyawaki