Abstract: A method is provided in which a base design is generated in the form of one or more data files including assignment data. A variation design is created by adding at least one additional assignment associated with the variation design to the assignment data. The assignment data has an identifier that is associated with an entity defined within the base design, a first data field that can be used in making an assignment to the entity within the base design and a second data field for use in making the additional assignment to the entity within the variation design. The data files are compiled to generate a base output file and one or more variation output design files that can include one or more common result values. Comparison data is generated by comparing the common result values associated with the base design file and the variation design file. A design tool is provided for use with a computer system having a processor. The design tool includes a selector and a variation mechanism.

Abstract: A technique for allowing local compilation at any level within a design hierarchy tree for a programmable logic device allows a user to compile within the context of the entire design using inherited parameter values and assignments from any parent nodes within the design hierarchy tree. A user is allowed to perform an isolated, local compilation that gives a compilation result as if the lower level node had been compiled within the context of the complete design. This local compilation is performed even though assignments, parameters, and logic options of parent nodes have not been compiled. An "action point" is specified at a node where a local compilation, timing analysis or simulation is to occur. A method compiles design source files that represent a PLD design. The design source files specify design entities that are represented as nodes in a design hierarchy tree. A first step analyzes the design source files to determine what design entities are represented in the source files.