Abstract: A semiconductor device is manufactured using a small amount of nitrogen in the gate electrode etch process to minimize notching at the bottom of the electrode. Consistent with one embodiment of the present invention, the gate electrode etch process includes using a plasma-etch and selectively etching into the device layer to form the electrode with its lower sidewalls protected using a relatively small percentage of nitrogen in the plasma gas flow.

Abstract: A process increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack. Formation of micro-trenches, while achieving nearly vertical profiles, is substantially minimized. In a method for manufacturing a semiconductor device gate stack a breakthrough etch removes residual oxide and anti-reflection coating until the layer of amorphous silicon is exposed. A bulk etch removes the amorphous silicon until about 40% remains. The remaining amorphous silicon layer is etched with a high selectivity etch until oxide is exposed. Any residual poly or amorphous silicon is etched with a very high-selectivity ratio over etch until clear.

Abstract: A process increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack, minimizing the formation of micro-trenches while achieving nearly vertical profiles. In an example embodiment, a method for manufacturing a semiconductor gate stack a gate stack having an anti-reflective coating, has a pattern defined with a photoresist mask The unmasked areas of the gate stack are etched with a first etch. The first etch removes the anti-reflective layer and a majority of the poly or amorphous silicon from the unmasked areas. After the first etch, the photoresist mask is removed. Using the anti-reflective coating as a hard mask the poly or amorphous silicon is removed with a second etch from unmasked areas until the gate oxide exposed. An over etch removes any poly or amorphous silicon residues.

Abstract: For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amorphous or poly silicon material can result in a localized breakthrough of the underlying thin gate oxide adjacent to the edge of the gate stack, especially in the N doped active regions. According to one example embodiment, this localized breakthrough (“microtrenching”) is avoided by building the gate stacks with undoped amorphous or poly silicon to the desired configuration, masking the gate stacks with a dielectric layer, planarizing the dielectric layer and then implanting the N-type or P-type species into the selected gate stack.

Abstract: For use with a sub-micron semiconductor process, a trench isolation process improves the etch profile of trenches among dense and isolated lines. In an example embodiment, a process forms a dielectric stack of silicon dioxide, silicon nitride and silicon oxynitride on a silicon substrate. Photolithography and etch define trench regions in the silicon substrate through the dielectric stack. Silicon oxynitride acts as a hard mask reducing differences in the sidewall slope among dense areas of the semiconductor device and the sparse areas of the semiconductor device.

Abstract: According to an example embodiment, the present invention is directed to a method for manufacturing a semiconductor device. The device includes a conductive underlayer. A sub-micron via or contact path and a dummy via or dummy contact path are dry etched. The endpoint of the dry etching process is optically detected, and the etching process is stopped responsive to the detection of the endpoint. By etching a dummy via or contact in addition to the submicron via or contact, this example embodiment facilitates endpoint detection for dry etching sub-micron features in semiconductor devices, which is otherwise difficult or even impossible in the submicron regime.

Abstract: A semiconductor device having metal interconnects provides for a reduction of the recessing of metal in vias, particularly when the metal in the vias is aluminum or an aluminum alloy. The device includes a via in a device layer of the semiconductor device, a barrier layer formed over the device layer, and a metal layer formed over the barrier layer. The metal layer also fills the via to form a via structure. A portion of the metal layer is then removed and a remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. A spacer is formed along the sidewall of the conductive structure and a portion of the barrier layer is removed using the spacer to protect the via structure adjacent the surface of the device layer. In particular, the spacer protects a portion of the via structure that does not overlap with the conductive structure.

Abstract: In modern sub-micron technologies with aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized, and electrical connections are less susceptible to electromigration. Consequently, device yield and reliability are increased.

Abstract: In modern sub-micron technologies with aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. By manipulating the etch chemistry so that the etch rates of the aluminum alloy, the surrounding barrier metals, and the dielectric are comparable, it is possible to perform the metal over etch without forming voids in the exposed portion of the via. By eliminating the voids, thinning of the vias due to the presence of recesses is minimized, and electrical connections are less susceptible to electromigration. Consequently, device yield and reliability are increased.

Abstract: A method of forming a semiconductor device minimizes oxide recessing in a trench of a semiconductor device. In one embodiment, forming a nitride spacer surrounding the top trench corner oxide in a shallow trench isolation region protects the corner oxide from being etched during processing. Oxide recessing in the trench is undesirable since it results in high electric fields around the sharp top corners of the trenches and Vt roll-off of the transistors. According to one example embodiment, STI regions filled with an HDP oxide and having undergone planarization, are masked. The masking substantially covers the HDP oxide and overlaps at least portions of nitride regions. Unmasked areas of the nitride regions are etched away forming nitride spacers on both sides of the HDP oxide fill.

Abstract: A process for manufacturing a semiconductor device having metal interconnects reduces or eliminates the recessing of metal in the vias, particularly when the metal in the vias is aluminum or an aluminum alloy. The process includes forming a via in a device layer of the semiconductor device. A barrier layer is formed over the device layer and a metal layer is formed over the barrier layer. The metal layer also fills the via to form a via structure. A portion of the metal layer is then removed and a remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. A spacer is formed along the sidewall of the conductive structure and a portion of the barrier layer is removed using the spacer to protect the via structure adjacent the surface of the device layer. In particular, the spacer protects a portion of the via structure that does not overlap with the conductive structure.

Abstract: A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At the end of the chemical mechanical polishing process, a portion of the insulating layer remains above the gate region. An etch process is performed to remove the portion of the insulating layer remaining above the gate region. The etch process also removes a portion of polysilicon within the gate region and removes a top portion of spacers on either side of the gate region. A polysilicon selective etch-back is performed to remove an additional portion of the polysilicon within the gate region.