Abstract: Disclosed herein is a comparator circuit including an amplifier including an auto zero operational amplifier and amplifying a difference between an input voltage and a predetermined first voltage, and a first voltage comparator comparing an output voltage of the amplifier with a predetermined second voltage.

Abstract: A time-to-digital converter circuit that measures a time difference between a first input signal and a second input signal includes: a jitter superimposition circuit that superimposes a jitter, which changes temporally, on one of the first input signal and the second input signal to generate a first intermediate signal and a second intermediate signal; a time-to-digital converter that measures a time difference between the first intermediate signal and the second intermediate signal each time the jitter changes; and a statistical processor that statistically processes a plurality of time differences measured by the time-to-digital converter in response to a plurality of jitters, and calculates a time difference between the first input signal and the second input signal.

Abstract: A method of controlling objects in an information processing system includes the steps of representing objects by a tree having a hierarchical structure, providing each of the objects with a first operation-target flag which indicates whether a corresponding object is a target of a given operation, and performing the given operation on an object upon receiving of an object handling request for the given operation only if the first operation-target flag of the object indicates that the object is a target of the given operation.

Abstract: A hierarchical processing system includes processors connected in a hierarchical formation having first, second and third hierarchical levels, for down loading information to the processors in parallel. The system comprises a memory unit provided at the first hierarchical level, for storing information to be down loaded to the processors located at the second and third hierarchical levels and for receiving configuration data about the processors located at the second and third hierarchical levels therefrom, a receiving unit provided at the second hierarchical level, for receiving the information to be down loaded to the processors located at the second and third hierarchical levels from the memory unit and for sending the configuration data about processors located at the second and third hierarchical levels to the memory unit.