Abstract: A decoding technique is disclosed for proving inexpensively a read channel circuit which has an error correction function and is applicable to high channel frequencies. In this read channel circuit, generating a reference slice level signal and a plurality of slice level signals which are different from the reference slice level signal, converting the playback signal into a plurality of binary signals synchronized with a channel clock according to each of the slice level signals, selecting two binary signals, measuring the phase distance between the two binary signals, judging the polarity of an inverted edge of a reference binary signal, and generating an error correction signal on the basis of the phase distance and the polarity of the inverted edge of the reference binary signal, whereby any error in the playback signal can be eliminated.

Abstract: A decoding technique is disclosed for proving inexpensively a read channel circuit which has an error correction function and is applicable to high channel frequencies. In this read channel circuit, generating a reference slice level signal and a plurality of slice level signals which are different from the reference slice level signal, converting the playback signal into a plurality of binary signals synchronized with a channel clock according to each of the slice level signals, selecting two binary signals, measuring the phase distance between the two binary signals, judging the polarity of an inverted edge of a reference binary signal, and generating an error correction signal on the basis of the phase distance and the polarity of the inverted edge of the reference binary signal, whereby any error in the playback signal can be eliminated.

Abstract: A data transfer system in which a programmable sequence controller, a computerized numerical controller and a pair of data transfer devices are associated respectively with the controllers. Each of the transfer devices includes a data memory and a first read-out and write-in circuit for exchanging control data between the data memory and the associated one of the controllers. Each of the transfer devices further includes a second read-out and write-in circuit which is enabled to operate when the first read-out and write-in circuit is inoperative, for exchanging control data between the data memory and the other controller, so that the control data is transferred from the sequence controller to the numerical controller, and vice versa.

Abstract: A feed control device is disclosed for controlling the feed speed of a tool relative to a workpiece to be machined. The device includes a load detector for generating an output signal in response to a load applied to the tool, a circuit responsive to the output signal generated by the load detector when the load is higher than a predetermined value for successively decreasing the feed speed until the load reaches the predetermined value, and a circuit responsive to the output signal generated by the load detector when the load is not more than the predetermined value for successively increasing the feed speed until the feed speed reaches a predetermined value.