Patents by Inventor Tamotsu Murakoshi
Tamotsu Murakoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11778827Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.Type: GrantFiled: July 6, 2022Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventors: Koichi Kawai, Yoshihiko Kamata, Yoshiaki Fukuzumi, Tamotsu Murakoshi
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Publication number: 20220359554Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Publication number: 20220336490Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.Type: ApplicationFiled: July 6, 2022Publication date: October 20, 2022Inventors: Koichi Kawai, Yoshihiko Kamata, Yoshiaki Fukuzumi, Tamotsu Murakoshi
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Patent number: 11398489Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: GrantFiled: September 4, 2020Date of Patent: July 26, 2022Assignee: Micron Technology, Inc.Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Patent number: 11393845Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.Type: GrantFiled: August 28, 2020Date of Patent: July 19, 2022Assignee: Micron Technology, Inc.Inventors: Koichi Kawai, Yoshihiko Kamata, Yoshiaki Fukuzumi, Tamotsu Murakoshi
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Publication number: 20220068953Abstract: A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Koichi Kawai, Yoshihiko Kamata, Yoshiaki Fukuzumi, Tamotsu Murakoshi
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Publication number: 20210005624Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: ApplicationFiled: September 4, 2020Publication date: January 7, 2021Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Patent number: 10770470Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: GrantFiled: March 13, 2017Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Publication number: 20170250190Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: ApplicationFiled: March 13, 2017Publication date: August 31, 2017Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Patent number: 9595533Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: GrantFiled: August 30, 2012Date of Patent: March 14, 2017Assignee: Micron Technology, Inc.Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Publication number: 20140061747Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.Type: ApplicationFiled: August 30, 2012Publication date: March 6, 2014Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
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Patent number: 7550838Abstract: A semiconductor device includes a first power supply which is disposed in a first direction, a first pad array which is disposed in the first direction, adjacent to the first power supply line, a second power supply line extending in the first direction, a first buffer circuit which is disposed between pads included in the first pad array, a second pad array which is disposed in the first direction, a third power supply line extending along the second pad array such that the second pad array is interposed between the second power supply line and the third power supply line, and a second buffer circuit which is disposed between pads included in the second pad array, and which is operated by a voltage between the second and third power supply lines.Type: GrantFiled: August 28, 2006Date of Patent: June 23, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Tamotsu Murakoshi
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Publication number: 20060289897Abstract: A semiconductor device includes a first power supply which is disposed in a first direction, a first pad array which is disposed in the first direction, adjacent to the first power supply line, a second power supply line extending in the first direction, a first buffer circuit which is disposed between pads included in the first pad array, a second pad array which is disposed in the first direction, a third power supply line extending along the second pad array such that the second pad array is interposed between the second power supply line and the third power supply line, and a second buffer circuit which is disposed between pads included in the second pad array, and which is operated by a voltage between the second and third power supply lines.Type: ApplicationFiled: August 28, 2006Publication date: December 28, 2006Inventor: Tamotsu Murakoshi