Abstract: A display panel driver includes: a latch block configured to latch a drive data signal corresponding to an image in response to assertion of a latch enable signal supplied externally and output the latched drive data signal as a first latch data signal; an output control block configured to delay the first latch data signal in response to the latch enable signal to generate a second latch data signal; and a drive circuit section configured to drive a wiring provided in a display panel in response to the second latch data signal. One of rising timing and falling timing of the second latch data signal outputted from the output control block is delayed from the other timing. The one timing is determined in response to negation of the latch enable signal, and the other timing is determined regardless of the negation of the latch enable signal.

Abstract: A display panel driver is provided with an output terminal to be connected to a data line of a display panel; a recovery capacitor connection terminal to be connected to a recovery capacitor; and a recovery switch connected between the output terminal and the recovery capacitor connection terminal. The recovery switch includes first and second MOS transistors of the same conductivity type. The drain of the first MOS transistor is connected to the recovery capacitor connection terminal, and the drain of the second MOS transistor is connected to the output terminal. The sources of the first and second MOS transistors are connected to each other.