Patents by Inventor Tamotsu Takeuchi

Tamotsu Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069469
    Abstract: An image forming apparatus includes a developer, a development device, and an image bearing member. The developer includes an initial developer containing an initial carrier and a replenishment developer containing a replenishment carrier. The initial carrier has a surface roughness Sa1 of at least 0.3 ?m and no greater than 1.0 ?m. A ratio Sa1/Sa2 of the surface roughness Sa1 of the initial carrier to a surface roughness Sa2 of the replenishment carrier is at least 1.2 and no greater than 3.4. The packing volume Vp calculated from equation (1)“Vp=100×Y/(Z×DS)” was at least 40% and no greater than 70%. In equation (1), Y represents an amount of the developer conveyed by a developer bearing member. Z represents an apparent density of the initial developer. DS represents a width of a space between the developer bearing member and the image bearing member.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 29, 2024
    Applicant: KYOCERA Document Solutions Inc.
    Inventors: Masashi FUJISHIMA, Tamotsu SHIMIZU, Asami SASAKI, Eriko TAKEUCHI
  • Patent number: 11422877
    Abstract: A method implemented by a computer including a plurality of components, each of the plurality of components including a processor configured to output an error notification after detecting an error, the method includes: executing a first processing when the error notification is received from an error detected processor, the first processing including specifying an error component by analyzing error information from the error detected processor; executing a second processing to issue a request for active exchange when another component able to be actively exchanged with the error component exists; executing a third processing to issue instructions in response to detecting that the operating system is alive after the issuing of the request, the instructions including a deletion instruction and an addition instruction, the deletion instruction being configured to execute active deletion processing of the error component, the addition instruction being configured to execute active addition processing of the othe
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 23, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Tamotsu Takeuchi
  • Publication number: 20220054445
    Abstract: The invention provides methods and compositions for treating cancer by administering to a patient in need thereof a therapeutically effective amount of 6,8-bis-benzylthio-octanoic acid and an autophagy inhibitor.
    Type: Application
    Filed: December 20, 2019
    Publication date: February 24, 2022
    Inventors: Timothy S. Pardee, Sanjeev Luther, Paul Bingham, Zuzana Zachar, Shawn D. Stuart, Robert G.L. Shorr, Tamotsu Takeuchi, Yusuke Kito, Chiemi Saigo
  • Publication number: 20210026726
    Abstract: A method implemented by a computer including a plurality of components, each of the plurality of components including a processor configured to output an error notification after detecting an error, the method includes: executing a first processing when the error notification is received from an error detected processor, the first processing including specifying an error component by analyzing error information from the error detected processor; executing a second processing to issue a request for active exchange when another component able to be actively exchanged with the error component exists; executing a third processing to issue instructions in response to detecting that the operating system is alive after the issuing of the request, the instructions including a deletion instruction and an addition instruction, the deletion instruction being configured to execute active deletion processing of the error component, the addition instruction being configured to execute active addition processing of the othe
    Type: Application
    Filed: July 20, 2020
    Publication date: January 28, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Tamotsu TAKEUCHI
  • Patent number: 9785599
    Abstract: A storage unit stores management information including information indicative of a correspondence relation between a plurality of devices and a plurality of peripheral devices and information indicative of a correspondence relation between identification information assigned to a peripheral device by a device and a position of the peripheral device. Upon receipt, from the device, of a notification that identification information of any peripheral device has been changed, a computation unit updates the management information in accordance with the content of the change. Upon acquisition of identification information of a target peripheral device from any device when the device outputs a log regarding the peripheral device, the computation unit provides the device with information indicative of a position of the peripheral device with reference to the management information.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: October 10, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Tamotsu Takeuchi
  • Patent number: 9672166
    Abstract: An information processing apparatus includes a storage unit and a processor. The storage unit stores a relationship between a device connected to the information processing apparatus and address information assigned to the device.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: June 6, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Tamotsu Takeuchi
  • Publication number: 20150356032
    Abstract: An information processing apparatus includes a storage unit and a processor. The storage unit stores a relationship between a device connected to the information processing apparatus and address information assigned to the device.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 10, 2015
    Inventor: Tamotsu TAKEUCHI
  • Publication number: 20150248369
    Abstract: A storage unit stores management information including information indicative of a correspondence relation between a plurality of devices and a plurality of peripheral devices and information indicative of a correspondence relation between identification information assigned to a peripheral device by a device and a position of the peripheral device. Upon receipt, from the device, of a notification that identification information of any peripheral device has been changed, a computation unit updates the management information in accordance with the content of the change. Upon acquisition of identification information of a target peripheral device from any device when the device outputs a log regarding the peripheral device, the computation unit provides the device with information indicative of a position of the peripheral device with reference to the management information.
    Type: Application
    Filed: May 18, 2015
    Publication date: September 3, 2015
    Inventor: Tamotsu TAKEUCHI
  • Patent number: 8677179
    Abstract: An information processing apparatus includes a degeneration control unit and a re-synchronization processing instructing unit. The degeneration control unit degenerates, of a first controller group including a first controller and a second controller group including a second controller, the second control device group when the first and second controller performing a synchronization operation with each other detect occurrence of errors. The re-synchronization processing instructing unit instructs a controller included in the first controller group to execute re-synchronization processing. When another controller different from the first controller receives the instruction for the execution of the re-synchronization processing, the another controller performs interrupt mask setting.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventor: Tamotsu Takeuchi
  • Publication number: 20120005525
    Abstract: An information processing apparatus includes a degeneration control unit and a re-synchronization processing instructing unit. The degeneration control unit degenerates, of a first controller group including a first controller and a second controller group including a second controller, the second control device group when the first and second controller performing a synchronization operation with each other detect occurrence of errors. The re-synchronization processing instructing unit instructs a controller included in the first controller group to execute re-synchronization processing. When another controller different from the first controller receives the instruction for the execution of the re-synchronization processing, the another controller performs interrupt mask setting.
    Type: Application
    Filed: September 2, 2011
    Publication date: January 5, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Tamotsu TAKEUCHI
  • Patent number: 7992056
    Abstract: There is provided an information processing apparatus that includes a CPU board 1 having a processing unit, a control device (CPU 11, CPU board controller 12, and the like) that is mounted on the CPU board 1 and includes hardware replacement management area 16 that stores replacement information indicating that the CPU board 1 has been replaced, the replacement information initialized at the time when the information processing apparatus is started or when the CPU board 1 is replaced, a memory 13 that stores error information based on occurrence of an error in the control device, the error information initialized at the time when the information processing apparatus is started, an initialization control section 18 that initializes the information processing apparatus, and a unit control section 45 that includes an error monitoring section 42 that monitors the error information stored in the memory 13 and controls the CPU board 1.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: August 2, 2011
    Assignee: Fujitsu Limited
    Inventor: Tamotsu Takeuchi
  • Publication number: 20090300433
    Abstract: There is provided an information processing apparatus that includes a CPU board 1 having a processing unit, a control device (CPU 11, CPU board controller 12, and the like) that is mounted on the CPU board 1 and includes hardware replacement management area 16 that stores replacement information indicating that the CPU board 1 has been replaced, the replacement information initialized at the time when the information processing apparatus is started or when the CPU board 1 is replaced, a memory 13 that stores error information based on occurrence of an error in the control device, the error information initialized at the time when the information processing apparatus is started, an initialization control section 18 that initializes the information processing apparatus, and a unit control section 45 that includes an error monitoring section 42 that monitors the error information stored in the memory 13 and controls the CPU board 1.
    Type: Application
    Filed: April 21, 2009
    Publication date: December 3, 2009
    Applicant: FUJITSU LIMITED
    Inventor: Tamotsu TAKEUCHI