Abstract: A semiconductor integrated circuit of the present invention features that a voltage is stably applied to a cell for high-speed operation and the number of lengthy wirings which run around a cell row is reduced without increasing a chip area, so that line efficiency can be improved. Since a power source line 16 and a ground line 17, each having a wide line running width, are formed on a top line layer above a cell 1 so as to cover nearly the whole surface of the cell 1, electrical resistance of the power source line 16 and the ground line 17 is reduced and then the voltage applied to the cell for high-speed operation is stabilized and such design is enabled without increasing the chip area. In addition, since penetrating lines 18 and 19 are formed on the lower line layer on a border between the cells, the number of lengthy lines which run around the cell row can be reduced by using the penetrating lines 18 and 19 as connecting between cells, so that line efficiency can be improved.

Abstract: A semiconductor integrated circuit includes a semiconductor chip having a predetermined circuit device and a PN junction diode group formed on the surface thereof. The PN junction diode group is supplied with a constant current in the forward direction, whereby the potential difference between the terminals thereof changes according to the surface temperature of the semiconductor chip. A potential difference generating circuit generates a fixed potential difference corresponding to a predetermined limit temperature of the chip surface, whereby the potential difference between the terminals of the PN junction diode group is compared with the fixed potential difference. As a result, when the determination in made that the temperature of the semiconductor chip surface reaches the limit temperature, the operation of the circuit device is temporarily or completely halted.