Patents by Inventor Tan-Chen Lee
Tan-Chen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9947758Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: GrantFiled: October 18, 2016Date of Patent: April 17, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
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Patent number: 9899494Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: GrantFiled: September 19, 2014Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
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Publication number: 20170040432Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: October 18, 2016Publication date: February 9, 2017Inventors: Tan-Chen Lee, Bor-Wen Chan
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Publication number: 20150044844Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: September 19, 2014Publication date: February 12, 2015Inventors: Tan-Chen Lee, Bor-Wen Chan
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Patent number: 8841192Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: GrantFiled: April 11, 2012Date of Patent: September 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
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Publication number: 20120196420Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: April 11, 2012Publication date: August 2, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
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Patent number: 8173540Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: GrantFiled: October 14, 2010Date of Patent: May 8, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
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Publication number: 20110027958Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: October 14, 2010Publication date: February 3, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Bor-Wen Chan
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Patent number: 7732298Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.Type: GrantFiled: January 31, 2007Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tan-Chen Lee, Chung-Te Lin, Kuang-Hsin Chen, Chi-Hsi Wu, Di-Houng Lee, Cheng-Hung Chang
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Patent number: 7432149Abstract: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the <100> direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the <110> direction, which is the direction where hole mobility is maximum for a {110} substrate.Type: GrantFiled: November 30, 2005Date of Patent: October 7, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Lu Wu, Chung-Te Lin, Tan-Chen Lee
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Publication number: 20080179689Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tan-Chen Lee, Chung-Te Lin, Kuang-Hsin Chen, Chi-Hsi Wu, Di-Houng Lee, Cheng-Hung Chang
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Publication number: 20070296052Abstract: A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.Type: ApplicationFiled: June 26, 2006Publication date: December 27, 2007Inventors: Tan-Chen Lee, Bor-Wen Chan
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Patent number: 7253071Abstract: Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer process, a strain compensating dielectric capping layer process during silicide formation, a two cycle anneal process during silicide formation, an excess nickel process to transform NiSi2 to NiSi.Type: GrantFiled: March 7, 2005Date of Patent: August 7, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Tan-Chen Lee
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Publication number: 20060292770Abstract: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the <100> direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the <110> direction, which is the direction where hole mobility is maximum for a {110} substrate.Type: ApplicationFiled: November 30, 2005Publication date: December 28, 2006Inventors: I-Lu Wu, Chung-Te Lin, Tan-Chen Lee
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Publication number: 20050272215Abstract: Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer process, a strain compensating dielectric capping layer process during silicide formation, a two cycle anneal process during silicide formation, an excess nickel process to transform NiSi2 to NiSi.Type: ApplicationFiled: March 7, 2005Publication date: December 8, 2005Inventor: Tan-Chen Lee