Patents by Inventor Tan Chong

Tan Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128163
    Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Patent number: 11942460
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Kelvin Tan Aik Boo, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye
  • Patent number: 11929351
    Abstract: An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Publication number: 20240072022
    Abstract: Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Seng Kim Ye, Kelvin Tan Aik Boo, Hong Wan Ng, Chin Hui Chong
  • Publication number: 20240071880
    Abstract: This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.
    Type: Application
    Filed: August 27, 2022
    Publication date: February 29, 2024
    Inventors: Seng Kim Ye, Kelvin Tan Aik Boo, Hong Wan Ng, Chin Hui Chong
  • Publication number: 20240072024
    Abstract: Modular systems in packages, and associated devices, systems, and methods, are disclosed herein. In one embodiment, a system comprises a main module package and an upper module package. The main module package includes a first substrate and a first electronic device mounted on a first side of the first substrate. The upper module package includes a second substrate and one or more second electronic devices mounted on a first side of the second substrate. The second substrate includes a cavity at a second side of the second substrate opposite the first side, and the upper module package is mountable on the first side of the first substrate of the main module package such that the first electronic device is positioned within the cavity and the second substrate generally surrounds at least a portion of a perimeter of the first electronic device.
    Type: Application
    Filed: August 27, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Hong Wan Ng, Seng Kim Ye, Chin Hui Chong
  • Publication number: 20060055666
    Abstract: In one embodiment, a method of operating a computer pointing peripheral comprises capturing images of a support surface to perform navigational analysis, analyzing at least one image characteristic, modifying an image exposure time in response to the analyzing, and modifying an intensity of illumination of the support surface when the image exposure time fails to satisfy an operating parameter.
    Type: Application
    Filed: September 14, 2004
    Publication date: March 16, 2006
    Inventors: Tan Chong, Liew Sen, Bernard Hock
  • Patent number: 5844614
    Abstract: A video signal decoding apparatus according to the present invention includes a decoding unit for applying a variable length and run-length decoding to a compressed video signal to reconstruct blocks of quantized coefficients. An inverse quantizer is provided for inverse quantizing blocks of reconstructed quantized coefficients. An inverse DCT transforms the inverse quantized blocks of reconstructed quantized coefficients to produce a decoded block. An edge block detector determines whether decoded blocks are classified as an edge block. An adaptive edge enhancement filter removes the distortion in the decoded blocks when the edge block detector classifies decoded blocks as edge blocks. Thus, the video signal is decoded from the encoded video signal.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: December 1, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Siew Tan Chong, Sheng Mei Shen, Chee Siong Khor
  • Patent number: 5488419
    Abstract: An input frame to be motion compensated is partitioned into smaller blocks of pixel data. First, motion estimation is performed on each block in full-pixel resolution. Then, full-pixel resolution motion vector is refined to half-pixel accuracy by searching the surrounding half-pixel resolution blocks in vertical and horizontal positions with respect to the full-pixel resolution motion vector. An absolute magnitude of a horizontal component of the full-pixel resolution motion vector is examined to see if it is greater or less than a predetermined threshold to detect any significant movement. If the horizontal component absolute magnitude is less than the threshold, a frame-based interpolation will be used for forming the sub-pixel resolution block. If the horizontal component absolute magnitude is greater than the threshold, a field-based interpolation will be used instead.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: January 30, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Lucas Y. W. Hui, Siew-Tan Chong