Abstract: The present invention is related to methods, processes, and systems that enable web users to quickly create, customize, and publish rich media contents via Internet. Web addresses and attributes with regard to the published rich media contents are also generated. The published rich media contents, web addresses and attributes are stored locally in a centralized place, but they can be called by any geographically distributed third-party websites or remote web users, and then be presented on the third-party websites or the terminal devices of the remote web users. Furthermore, the present invention also enables web users to quickly create and customize personal online stores at a centralized place, and then list the published rich media contents in their personal online stores.

Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.

Abstract: A circuit (90) and method are presented to accurately determine a BEMF voltage of a VCM coil (20) after termination of a driving current in a first current direction in the coil (20). The circuit includes a circuit for activating selected VCM coil driver transistors (44–47) to apply a current to the coil (20) in a direction opposite the first current direction to generate a magnetic field to oppose eddy currents established in structures adjacent the coil (20) by the driving current. The time that the eddy current opposing current may be applied may be determined, for example, by determining a magnitude of the original current command, a time that the coil spends in flyback, or a magnitude of the original driving current, and adjusting the time of application of the eddy current opposing current accordingly.

Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.

Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.

Abstract: Disclosed are methods, systems, and algorithms for accurately measuring a DC voltage signal (Vin) using a sigma-delta modulator (36). The preferred embodiments disclose determining a fundamental period (Tp) of the pattern noise cycle of sigma-delta modulator output at a given DC input (Vin), and mapping a one-to-one relationship to the ratio of Vin to reference voltage (Vref). Methods, systems, and algorithms according to the invention include the conversion of a DC input (Vin) into a digital bitstream that periodically provides low-resolution high-frequency digital words (D1) representative of the DC input (Vin). The low-resolution high-frequency words (D1) are in turn periodically converted into high-resolution low-frequency words (D2) representative of the DC input (Vin).

Abstract: The present invention provides an improved model and methodology for simulating motor performance which allow increased control accuracy at the higher currents, higher speeds, and/or higher current change rates required in modem mass storage devices. In addition, the invention provides methods for simulating motor performance, and for testing a motor commutation scheme. The model includes a plurality of phases extending between first ends joined at a center tap and second ends extending outward from the center tap to a corresponding plurality of phase taps, and a mutual inductance component disposed between two of the phases, wherein the mutual inductance and/or the phase inductance components may be a function of rotor position and/or current.

Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.

Abstract: Disclosed are methods, systems, and algorithms for accurately measuring a DC voltage signal (Vin) using a sigma-delta modulator (36). The preferred embodiments disclose determining a fundamental period (Tp) of the pattern noise cycle of sigma-delta modulator output at a given DC input (Vin), and mapping a one-to-one relationship to the ratio of Vin to reference voltage (Vref). Methods, systems, and algorithms according to the invention include the conversion of a DC input (Vin) into a digital bitstream that periodically provides low-resolution high-frequency digital words (D1) representative of the DC input (Vin). The low-resolution high-frequency words (D1) are in turn periodically converted into high-resolution low-frequency words (D2) representative of the DC input (Vin).

Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.

Abstract: A circuit model (50) for use in analyzing a VCM circuit has a first resistor (62), a first inductor (64), a second inductor (58), and a voltage source (60), in series modeling, respectively, a VCM inductor, a winding leakage inductance of the VCM inductor, a VCM inductor resistance, and a BEMF voltage generated across the VCM inductor when the input nodes are open circuited. An input capacitor (56) interconnects the input terminals (52,54) to model an equivalent capacitance of the VCM inductor. Third and fourth inductors (32,34) and a second resistor (36) are connected in a first series loop (28) inductively coupled to the second inductor (58) to model, respectively, an inductance of the top VCM magnet plate, the leakage inductance of the top VCM magnet plate, and a resistance of the top VCM magnet plate.

Abstract: The invention provides an algorithm for systematically determining and optimizing the physical implementation of an array of networks with a combination of matching series and parallel elements. Disclosed are the machine-implemented steps of defining the network in terms of a network value representing the sum of the elements. The network value is divided into an integer part and a proper fraction part. A partial quotient and residue are computed for the proper fraction part. Additional partial quotients and residues may be computed while the residue is significant. The physical implementation of the network is then described in terms of series and parallel elements represented by the integer part and the partial quotients. Also disclosed is a method of assembling a network from a combination of series and parallel elements. A network value consisting of an integer part and a proper fraction part are used to represent the network.

Abstract: The invention provides an algorithm for systematically determining and optimizing the physical implementation of an array of networks with a combination of matching series and parallel elements. Disclosed are the machine-implemented steps of defining the network in terms of a network value representing the sum of the elements. The network value is divided into an integer part and a proper fraction part. A partial quotient and residue are computed for the proper fraction part. Additional partial quotients and residues may be computed while the residue is significant. The physical implementation of the network is then described in terms of series and parallel elements represented by the integer part and the partial quotients. Also disclosed is a method of assembling a network from a combination of series and parallel elements. A network value consisting of an integer part and a proper fraction part are used to represent the network.

Abstract: Disclosed are systems, methods, and algorithms for network layout. A network layout having subnetworks of matching series and parallel elements is systematically generated to implement the network within area constraints. After the selection of the number of rows of network elements, the number of elements in each row, the sequencing of the elements, and the element locations, are systematically determined. The network layout systematically produced reduces the influence of unfavorable factors on the network such as temperature gradients, process gradients, and interference, by dispersing subnetwork elements throughout the layout.

Abstract: The invention includes a method and apparatus for detecting the position of a stationary rotor in a polyphase electric motor. The method includes providing one or more short duration voltage pulses to the motor and determining the rotor position based on measurements of one or more phase voltages. The invention allows identification of a region in which the rotor is positioned, through polarity sensing, whereby the rotor position may be quickly and accurately determined, to allow a stationary electric motor to be properly energized to rotate in a desired direction.

Abstract: Disclosed are systems, methods and algorithms for simulating a Linear Time Invariant (LTI) system, such as a circuit, using an iterative model. A settle time is determined for a LTI system. Standard step response data is collected reflecting the step response of the system for a period equal to the settle time. A particular section of standard step response data is then used for modeling the LTI system for an arbitrary input and providing simulated output results.

Abstract: Disclosed are methods, systems, and algorithms for simulating a system, such as a circuit, using an iterative model. Standard step response data is used for modeling the system and providing simulation results. Disclosed are simulation engines employing dynamically adjusted sample sizes and event scheduling. Also disclosed is the use of an approximation of the first order derivative of the simulation input to obtain the expected error for use in dynamically adjusting the step size. The use of an approximation of the second order derivative of the simulation input is also disclosed. The use of embodiments of the simulation engine with particular iterative models is described.

Abstract: Disclosed are systems and methods for realizing a selected semiconductor device design using a virtual IC to model the design and simulate characterization and testing for further development of the design prior to the fabrication of actual semiconductor devices. According to the disclosed embodiments of the invention, a common platform may be used for design and simulation phases of IC development.

Abstract: The invention includes a method and apparatus for detecting the position of an electric motor rotor by sensing the zero crossing or polarity change of a mutual inductance associated with the motor. The use of mutual inductance provides for consistent position detection unaffected by motor speed or winding current, thus providing significant advantages over traditional back emf zero crossing detection methods. The mutual inductance zero crossing may be detected by measuring a voltage signal in a floating phase of the motor, filtering back emf and excitation components out of the measured voltage signal, and detecting a polarity change or zero crossing in the resulting mutual inductance signal.

Abstract: A method for characterizing a VCM assembly includes measuring a first response of the VCM assembly (100), removing a first conducting part of the VCM assembly (102), and measuring a second response of the VCM assembly with the first conducting part removed (104). Then, the method includes using curve fitting techniques (110) with the determined VCM compensation parameters to construct a model of the VCM assembly.