Abstract: A data processing system (10) includes a CPU (12) and debug circuitry (16). CPU (12) can execute instructions which provide direct input to one or more of trigger circuitry (32), multi-function debug counters (34), combining logic (36), and action select and control logic (38). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger (117) can produce a resulting action or trigger (119) but only if it occurs in a predetermined order compared to one or more other triggers (117). Multi-function debug counters (34) can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.

Abstract: A data processing system (10) includes a CPU (12) and debug circuitry (16). CPU (12) can execute instructions which provide direct input to one or more of trigger circuitry (32), multi-function debug counters (34), combining logic (36), and action select and control logic (38). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger (117) can produce a resulting action or trigger (119) but only if it occurs in a predetermined order compared to one or more other triggers (117). Multi-function debug counters (34) can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.

Abstract: A data processing system (10) includes a CPU (12) and debug circuitry (16). CPU (12) can execute instructions which provide direct input to one or more of trigger circuitry (32), multi-function debug counters (34), combining logic (36), and action select and control logic (38). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger (117) can produce a resulting action or trigger (119) but only if it occurs in a predetermined order compared to one or more other triggers (117). Multi-function debug counters (34) can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.

Abstract: A data processing system (10) includes a CPU (12) and debug circuitry (16). CPU (12) can execute instructions which provide direct input to one or more of trigger circuitry (32), multi-function debug counters (34), combining logic (36), and action select and control logic (38). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger (117) can produce a resulting action or trigger (119) but only if it occurs in a predetermined order compared to one or more other triggers (117). Multi-function debug counters (34) can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.

Abstract: A data processing system (10) includes a CPU (12) and debug circuitry (16). CPU (12) can execute instructions which provide direct input to one or more of trigger circuitry (32), multi-function debug counters (34), combining logic (36), and action select and control logic (38). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger (117) can produce a resulting action or trigger (119) but only if it occurs in a predetermined order compared to one or more other triggers (117). Multi-function debug counters (34) can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.

Abstract: Data block identification within a processor 100 may be accomplished when the processor 100 receives an interrupt while performing a main set of operational codes. Upon receiving the interrupt, the processor 100 determines whether the interrupt is of a fast interrupt type. When the interrupt if of a fast interrupt type, the processor executes the operational codes identified by the interrupt without having to flag the main set of operational codes. Upon completion of the fast interrupt, the processor 100 resumes performing the main set of operational codes. In addition to performing the fast interrupt, the processor 100 contemporaneously performs a data block identification routine. When the data block identification routine identifies a data block, the main set of operational codes is interrupted to perform a data block service routine. The processor 100 includes an address generation unit 102 and a peripheral address generation unit 104.

Abstract: A method and apparatus for an improving memory access bandwidth that can be used in a digital signal processor (DSP) (500) is accomplished by modifying addresses (302, 304) generated by an address generation unit (AGU) (102) of the DSP (500). Two addresses (302, 304) are generated by the AGU (102). One of the two addresses (302) is used to address two parallel memory blocks (308, 310) in a single memory simultaneously, and the other address (304) is modified by a modulo increment function to produce two additional addresses (404, 406) that also address the parallel memory blocks (308, 310). With such a method and apparatus, four simultaneous memory reads can occur, effectively doubling the memory access bandwidth in the DSP system (500) without modification of the AGU (102) or program controller (510).

Abstract: A data processing system (10) and associated method (150) of operation selectively compand data on a slot-by-slot basis. The data processing system (10) includes a processor (12), processor bus (14), memory (16), output serial interface (18), and input serial interface (70). The output serial interface (18) includes an output data buffer (20), compression module (22), output shift register (24), and output controller (26). In operation, the output serial interface (18) receives output data (28) and selectively compresses the data on a slot-by-slot basis. The shift register (24) then places the transmit data (32) on the serial link (25). An input serial interface (128) selectively expands data received on the serial link (25) on a slot-by-slot basis to produce input data (82). The associated method (150) includes method steps for companding data on a slot-by-slot basis. An ISDN interface and digital telephone (200) employ the teachings of the present invention.