Patents by Inventor Tan Pee Ya

Tan Pee Ya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Triggered silicon controlled rectifier for RF ESD protection
    Patent number: 8134211
    Abstract: An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: March 13, 2012
    Assignees: GLOBALFOUNDRIES Singapore Pte, Ltd., Agilent Technologies, Inc.
    Inventors: Indrajit Manna, Lo Keng Foo, Tan Pee Ya, Raymond Filippi
  • TRIGGERED SILICON CONTROLLED RECTIFIER FOR RF ESD PROTECTION
    Publication number: 20100001283
    Abstract: An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
    Type: Application
    Filed: September 14, 2009
    Publication date: January 7, 2010
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., AGILENT TECHNOLOGIES, INC.
    Inventors: Indrajit Manna, Lo Keng Foo, Tan Pee Ya, Raymond Filippi
  • Triggered silicon controlled rectifier for RF ESD protection
    Patent number: 7615417
    Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: November 10, 2009
    Assignees: Chartered Semiconductor Manufacturing Ltd., Agilent Technologies, Inc.
    Inventors: Indrajit Manna, Lo Keng Foo, Tan Pee Ya, Raymond Filippi
  • Method for forming an ESD protection circuit
    Patent number: 7285458
    Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: October 23, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Indrajit Manna, Lo Keng Foo, Tan Pee Ya, Raymond Filippi