Patents by Inventor Tan Xiaochun
Tan Xiaochun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8288200Abstract: A semiconductor device is described that includes a die connected between a conductive platform and a conductive clip. The semiconductor device is formed by a process that includes mounting a first surface of each of multiple die to each of a number of conductive mounting platforms of a lead frame structure. The process also mounts a clip structure to the lead frame structure, the clip structure including a number of conductive clips. Mounting of the clip structure to the lead frame structure includes aligning each of the conductive clips with corresponding ones of the conductive mounting platforms so that a portion of each of the conductive clips contacts a second surface of a corresponding die.Type: GrantFiled: November 30, 2005Date of Patent: October 16, 2012Assignee: Diodes Inc.Inventor: Tan Xiaochun
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Patent number: 7960209Abstract: A Conductive Epoxy Coating (“CEC”) process is provided for assembling semiconductor devices. The CEC process includes application of a conductive epoxy coating prior to wafer dicing and instead of dispensing epoxy/solder when performing die bonding. The CEC process generally begins with a silicon wafer. Processing of the silicon wafer includes coupling a conductive epoxy layer to a first side of the semiconductor wafer to form a coated wafer. The process cures the coated wafer and forms die from the coated wafer. The process further couples an exposed side of the conductive epoxy layer of the die to a lead frame to form a semiconductor device, and cures the semiconductor device.Type: GrantFiled: January 31, 2005Date of Patent: June 14, 2011Assignee: Diodes, Inc.Inventors: Tan Xiaochun, Jiang Xiaolan
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Patent number: 7834433Abstract: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level of the lead frame. A molding compound encapsulates the semiconductor die and a portion of the lead frame, such that a portion of the heat sink is outside of the molding compound. The resulting device may be efficiently manufactured as compared to dual gauge lead frame devices or devices where the semiconductor die is not attached to the lead frame.Type: GrantFiled: July 16, 2007Date of Patent: November 16, 2010Assignee: Shanghai Kaihong Technology Co., Ltd.Inventors: Tan Xiaochun, Li Yunfang
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Patent number: 7786555Abstract: A semiconductor device that includes multiple heat sinks is provided along with methods for forming a semiconductor device having multiple heat sinks. The semiconductor device includes a first heat sink that is configured as a conductive lead frame. The conductive lead frame is electrically coupled to a conducting area of a semiconductor die. The semiconductor device also includes a second heat sink that is configured as a conductive clip. The conductive clip is electrically coupled to another conducting area of the die. Alternative embodiments of the device may include more than two heat sinks.Type: GrantFiled: October 20, 2005Date of Patent: August 31, 2010Assignee: Diodes, IncorporatedInventor: Tan Xiaochun
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Patent number: 7682874Abstract: In one embodiment the present invention includes a method of fabricating a chip scale package (CSP). The method includes forming conductive bumps on a top side of a semiconductor wafer; mounting the top side of the semiconductor wafer on adhesive tape; sawing the semiconductor wafer a first time such that a wide sawing kerf is obtained; molding the semiconductor wafer with a molding compound; and sawing the semiconductor wafer a second time to obtain the CSPs. Such method has improved efficiency as compared to many existing methods of fabricating CSPs.Type: GrantFiled: July 10, 2006Date of Patent: March 23, 2010Assignee: Shanghai KaiHong Technology Co., Ltd.Inventors: Tan Xiaochun, Li Yunfang
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Patent number: 7402459Abstract: In one embodiment the present invention includes a method of fabricating a quad flat no-lead (QFN) chip package. The method includes forming a stamped lead frame; forming a die pad and a lead shrink on one side of the stamped lead frame; mounting a die on the die pad; performing wire bonding; encapsulating the die and the wire bond with a molding compound; removing the stamped lead frame after encapsulating; and sawing the molding compound after the stamped lead frame has been removed. Such method results in improved quality of wire leads, improved lifespan of cutting blades, and reduction of burrs as compared to many existing methods of fabricating QFN chip packages.Type: GrantFiled: July 10, 2006Date of Patent: July 22, 2008Assignee: Shanghai Kaihong Technology Co., Ltd.Inventors: Tan Xiaochun, Li Yunfang
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Publication number: 20080164590Abstract: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level of the lead frame. A molding compound encapsulates the semiconductor die and a portion of the lead frame, such that a portion of the heat sink is outside of the molding compound. The resulting device may be efficiently manufactured as compared to dual gauge lead frame devices or devices where the semiconductor die is not attached to the lead frame.Type: ApplicationFiled: July 16, 2007Publication date: July 10, 2008Applicant: Diodes, Inc.Inventors: Tan Xiaochun, Li Yunfang
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Publication number: 20080014677Abstract: In one embodiment the present invention includes a method of fabricating a chip scale package (CSP). The method includes forming conductive bumps on a top side of a semiconductor wafer; mounting the top side of the semiconductor wafer on adhesive tape; sawing the semiconductor wafer a first time such that a wide sawing kerf is obtained; molding the semiconductor wafer with a molding compound; and sawing the semiconductor wafer a second time to obtain the CSPs. Such method has improved efficiency as compared to many existing methods of fabricating CSPs.Type: ApplicationFiled: July 10, 2006Publication date: January 17, 2008Inventors: Tan Xiaochun, Li Yunfang
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Publication number: 20080009103Abstract: In one embodiment the present invention includes a method of fabricating a quad flat no-lead (QFN) chip package. The method includes forming a stamped lead frame; forming a die pad and a lead shrink on one side of the stamped lead frame; mounting a die on the die pad; performing wire bonding; encapsulating the die and the wire bond with a molding compound; removing the stamped lead frame after encapsulating; and sawing the molding compound after the stamped lead frame has been removed. Such method results in improved quality of wire leads, improved lifespan of cutting blades, and reduction of burrs as compared to many existing methods of fabricating QFN chip packages.Type: ApplicationFiled: July 10, 2006Publication date: January 10, 2008Inventors: Tan Xiaochun, Li Yunfang
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Patent number: 7264999Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.Type: GrantFiled: May 26, 2006Date of Patent: September 4, 2007Assignee: Diodes, Inc.Inventors: Tan Xiaochun, Shi Jingping
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Publication number: 20070123073Abstract: A semiconductor device is described that includes a die connected between a conductive platform and a conductive clip. The semiconductor device is formed by a process that includes mounting a first surface of each of multiple die to each of a number of conductive mounting platforms of a lead frame structure. The process also mounts a clip structure to the lead frame structure, the clip structure including a number of conductive clips. Mounting of the clip structure to the lead frame structure includes aligning each of the conductive clips with corresponding ones of the conductive mounting platforms so that a portion of each of the conductive clips contacts a second surface of a corresponding die.Type: ApplicationFiled: November 30, 2005Publication date: May 31, 2007Inventor: Tan Xiaochun
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Publication number: 20070090463Abstract: A semiconductor device that includes multiple heat sinks is provided along with methods for forming a semiconductor device having multiple heat sinks. The semiconductor device includes a first heat sink that is configured as a conductive lead frame. The conductive lead frame is electrically coupled to a conducting area of a semiconductor die. The semiconductor device also includes a second heat sink that is configured as a conductive clip. The conductive clip is electrically coupled to another conducting area of the die. Alternative embodiments of the device may include more than two heat sinks.Type: ApplicationFiled: October 20, 2005Publication date: April 26, 2007Inventor: Tan Xiaochun
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Publication number: 20060214290Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.Type: ApplicationFiled: May 26, 2006Publication date: September 28, 2006Inventors: Tan Xiaochun, Shi Jingping
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Patent number: 7095113Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.Type: GrantFiled: January 31, 2005Date of Patent: August 22, 2006Assignee: Diodes IncorporatedInventors: Tan Xiaochun, Shi Jingping
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Publication number: 20050199985Abstract: A semiconductor device is provided having a single-piece clip that interlocks into a lead frame using one or more forks on the clip that mate with one or more corresponding slots in the lead frame. A semiconductor die is mounted to a pad of the lead frame and the clip couples the die to a conductive lead of the lead frame. The interlocking coupling forms a lever that allows adjustment of a position of the clip relative to a region of the semiconductor die. Interference between the clip fork and a slot corresponding to the clip fork confines the lever motion or pivoting of the clip relative to the mounted semiconductor die. The coupling between the clip fork and the slot furthermore confines motion of the clip in each of a first dimension and a second dimension relative to a position of the lead frame.Type: ApplicationFiled: January 31, 2005Publication date: September 15, 2005Inventors: Tan Xiaochun, Shi Jingping
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Publication number: 20050189626Abstract: A semiconductor device is provided that includes a platform having an interior surface and an exterior conductive surface. The exterior conductive surface includes an indentation or notch in a portion of one or more edges. The device also includes a die that electrically couples to the interior surface of the platform, along with one or more clips that couple a conductive area of the die to one or more conductive leads. A package enclosure encapsulates the interior surface of the platform, the die, the clip, and portions of the conductive lead. The package enclosure engages the indentation in the exterior conductive surface and secures the package enclosure to the platform.Type: ApplicationFiled: January 31, 2005Publication date: September 1, 2005Inventors: Tan Xiaochun, Shi Jingping
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Publication number: 20050189658Abstract: A Conductive Epoxy Coating (“CEC”) process is provided for assembling semiconductor devices. The CEC process includes application of a conductive epoxy coating prior to wafer dicing and instead of dispensing epoxy/solder when performing die bonding. The CEC process generally begins with a silicon wafer. Processing of the silicon wafer includes coupling a conductive epoxy layer to a first side of the semiconductor wafer to form a coated wafer. The process cures the coated wafer and forms die from the coated wafer. The process further couples an exposed side of the conductive epoxy layer of the die to a lead frame to form a semiconductor device, and cures the semiconductor device.Type: ApplicationFiled: January 31, 2005Publication date: September 1, 2005Inventors: Tan Xiaochun, Jiang Xiaolan