Patents by Inventor Tan-Ya Yin
Tan-Ya Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446663Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first fin segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.Type: GrantFiled: September 4, 2018Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tan-Ya Yin, Chia-Wei Huang
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Publication number: 20190013394Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.Type: ApplicationFiled: September 4, 2018Publication date: January 10, 2019Inventors: Tan-Ya Yin, Chia-Wei Huang
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Patent number: 10153034Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.Type: GrantFiled: March 3, 2017Date of Patent: December 11, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
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Publication number: 20180308954Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a patterned conductive layer and an epitaxial layer. The substrate includes a first fin structure and a second fin structure respectively protruding from a top surface of the substrate, and the second fin structure has a recess. The patterned conductive layer is disposed on the substrate and covers a first end of the first fin structure. The epitaxial layer is disposed in the recess. The first end of the first fin structure and a second end of the epitaxial layer face a first direction.Type: ApplicationFiled: June 9, 2017Publication date: October 25, 2018Inventors: Tan-Ya Yin, Chia-Wei Huang
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Patent number: 10109720Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a patterned conductive layer and an epitaxial layer. The substrate includes a first fin structure and a second fin structure respectively protruding from a top surface of the substrate, and the second fin structure has a recess. The patterned conductive layer is disposed on the substrate and covers a first end of the first fin structure. The epitaxial layer is disposed in the recess. The first end of the first fin structure and a second end of the epitaxial layer face a first direction.Type: GrantFiled: June 9, 2017Date of Patent: October 23, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tan-Ya Yin, Chia-Wei Huang
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Patent number: 9859170Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.Type: GrantFiled: February 16, 2017Date of Patent: January 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
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Publication number: 20170178716Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.Type: ApplicationFiled: March 3, 2017Publication date: June 22, 2017Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
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Publication number: 20170162449Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
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Patent number: 9627036Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.Type: GrantFiled: August 11, 2015Date of Patent: April 18, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
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Patent number: 9613969Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.Type: GrantFiled: July 7, 2015Date of Patent: April 4, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
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Publication number: 20170018302Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.Type: ApplicationFiled: August 11, 2015Publication date: January 19, 2017Inventors: Tan-Ya Yin, Ming-Jui Chen, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang
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Publication number: 20160351575Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.Type: ApplicationFiled: July 7, 2015Publication date: December 1, 2016Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
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Patent number: 9368365Abstract: A manufacturing method for forming a semiconductor structure includes: first, a plurality of fin structures are formed on a substrate and arranged along a first direction, next, a first fin cut process is performed, so as to remove parts of the fin structures which are disposed within at least one first fin cut region, and a second fin cut process is then performed, so as to remove parts of the fin structures which are disposed within at least one second fin cut region, where the second fin cut region is disposed along at least one edge of the first fin cut region.Type: GrantFiled: May 12, 2015Date of Patent: June 14, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hsun Kuo, Ting-Cheng Tseng, Tan-Ya Yin, Chia-Wei Huang, Ming-Jui Chen