Patents by Inventor Tanausu Ramirez
Tanausu Ramirez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220131998Abstract: Certain examples relate to a method of color prediction. Data indicative of color characteristics measured from a number of color test patches is obtained. Data indicative of combinations of color resources used to render the color test patches on a color rendering device is obtained. A first predictive model is trained using the data indicative of the combinations of color resources as an input and corresponding data indicative of color characteristics as ground truth outputs. A second predictive model is trained using the output data from the first predictive model as an input and the corresponding data indicative of color characteristics as ground truth outputs. A progressive mapping is implemented by the first and second predictive models to predict color characteristics rendered by the color rendering device given a combination of color resources.Type: ApplicationFiled: July 15, 2019Publication date: April 28, 2022Applicant: Hewlett-Packard Development Company, L.P.Inventors: Peter Morovic, Jan Morovic, Sergio Etchebehere Juan, Tanausu Ramirez Garcia, Hector Gomez Minano
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Patent number: 10440195Abstract: A method of determining calibration values for a media advance system of a page wide array printing device is described. A test pattern is printed on a calibration medium which advances along a media axis through the printing device. The test pattern comprises a plurality of test marks. The test pattern is scanned along a scan axis using a sensor and the calibration medium is advanced along the media axis through the printing device. The dimensions of the scanned test marks are analyzed, and calibration values are determined from the analyzed dimensions of the test marks. The scan axis is orthogonal to the media axis.Type: GrantFiled: October 30, 2015Date of Patent: October 8, 2019Assignee: Hewlett-Packard Development Company, L.P.Inventors: Alberto Borrego Lebrato, Francisco Javier Roses Conesa, Tanausu Ramirez, Isidoro Maya
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Publication number: 20180220013Abstract: A method of determining calibration values for a media advance system of a page wide array printing device is described. A test pattern is printed on a calibration medium which advances along a media axis through the printing device. The test pattern comprises a plurality of test marks. The test pattern is scanned along a scan axis using a sensor and the calibration medium is advanced along the media axis through the printing device. The dimensions of the scanned test marks are analyzed, and calibration values are determined from the analyzed dimensions of the test marks. The scan axis is orthogonal to the media axis.Type: ApplicationFiled: October 30, 2015Publication date: August 2, 2018Inventors: Alberto Borrego Lebrato, Fco. Javier Roses, Tanausu Ramirez, Isidoro Maya
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Patent number: 9983880Abstract: An apparatus and method are described for improved thread selection. For example, one embodiment of a processor comprises: first logic to maintain a history table comprising a plurality of entries, each entry in the table associated with an instruction and including history data indicating prior hits and/or misses to a cache level and/or a translation lookaside buffer (TLB) for that instruction; and second logic to select a particular thread for execution at a particular processor pipeline stage based on the history data.Type: GrantFiled: September 26, 2014Date of Patent: May 29, 2018Assignee: Intel CorporationInventors: Rekai Gonzalez-Alberquilla, Tanausu Ramirez, Josep M. Codina, Enric Gibert Codina
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Publication number: 20170201459Abstract: An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Inventors: MATTEO MONCHIERO, JAVIER CARRETERO CASADO, ENRIC HERRERO ABELLANAS, TANAUSU RAMIREZ, XAVIER VERA
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Patent number: 9619309Abstract: A method of an aspect includes determining a different operational configuration for each of a plurality of different maximum failure rates. Each of the different maximum failure rates corresponds to a different task of a plurality of tasks. The method also includes enforcing a plurality of logic each executing a different task of the plurality of tasks to operate according to the different corresponding determined operational configuration. Other methods, apparatus, and systems are also disclosed.Type: GrantFiled: December 28, 2012Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Enric H. Abellanas, Xavier Vera, Nicholas Axelos, Javier C. Casado, Tanausu Ramirez, Daniel Sanchez PedreƱo
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Patent number: 9608922Abstract: An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.Type: GrantFiled: December 23, 2011Date of Patent: March 28, 2017Assignee: Intel CorporationInventors: Matteo Monchiero, Javier Carretero Casado, Enric Herrero Abellanas, Tanausu Ramirez, Xavier Vera
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Publication number: 20160342495Abstract: Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.Type: ApplicationFiled: August 2, 2016Publication date: November 24, 2016Inventors: XAVIER VERA, JAVIER CARRETERO CASADO, MATTEO MONCHIERO, TANAUSU RAMIREZ, ENRIC HERRERO ABELLANAS
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Patent number: 9405647Abstract: Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.Type: GrantFiled: December 30, 2011Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Xavier Vera, Javier Carretero Casado, Matteo Monchiero, Tanausu Ramirez, Enric Herrero
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Publication number: 20160092235Abstract: An apparatus and method are described for improved thread selection. For example, one embodiment of a processor comprises: first logic to maintain a history table comprising a plurality of entries, each entry in the table associated with an instruction and including history data indicating prior hits and/or misses to a cache level and/or a translation lookaside buffer (TLB) for that instruction; and second logic to select a particular thread for execution at a particular processor pipeline stage based on the history data.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: REKAI GONZALEZ-ALBERQUILLA, TANAUSU RAMIREZ, JOSEP M. CODINA, ENRIC GIBERT CODINA
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Patent number: 9286172Abstract: Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.Type: GrantFiled: December 22, 2011Date of Patent: March 15, 2016Assignee: Intel CorporationInventors: Tanausu Ramirez, Javier Carretero Casado, Enric Herrero, Matteo Monchiero, Xavier Vera
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Publication number: 20160011874Abstract: A processing device implementing silent memory instructions and miss-rate tracking to optimize switching policy on threads is disclosed. A processing device of the disclosure includes a branch prediction unit (BPU) to predict that an instruction of a first thread in a current execution context of the processing device is a delinquent instruction, indicate that the first thread including the delinquent instruction is in a silent execution mode, indicate that the delinquent instruction is to be executed as a silent instruction, switch an execution context of the processing device to a second thread, and when the execution context returns to the first thread, cause the delinquent instruction to be re-executed as a regular instruction.Type: ApplicationFiled: July 9, 2014Publication date: January 14, 2016Inventors: DORON ORENSTEIN, TOMER STARK, CHEN DAN, JACOB DOWECK, ENRIC G. CODINA, JOSEP M. CODINA, REKAI GONZALEZ-ALBERQUILLA, TANAUSU RAMIREZ
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Patent number: 9176895Abstract: A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.Type: GrantFiled: March 16, 2013Date of Patent: November 3, 2015Assignee: Intel CorporationInventors: Xavier Vera, Javier Carretero Casado, Enric Herrero Abellanas, Daniel Sanchez, Nicholas Axelos, Tanausu Ramirez
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Patent number: 9170947Abstract: Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache.Type: GrantFiled: December 29, 2011Date of Patent: October 27, 2015Assignee: Intel CorporationInventors: Xavier Vera, Matteo Monchiero, Javier Carretero Casado, Enric Herrero, Tanausu Ramirez
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Patent number: 9112537Abstract: Embodiments of systems, apparatuses, and methods for reducing data cache power consumption and error protection overhead are described. In some embodiments, the data cache is partitioned into cache portions. Each cache portion stores data that has a different fault tolerance and uses a different type of error detection mechanism than the other cache portions.Type: GrantFiled: December 22, 2011Date of Patent: August 18, 2015Assignee: Intel CorporationInventors: Tanausu Ramirez, Javier Carretero Casado, Enric Herrero, Matteo Monchiero, Xavier Vera
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Patent number: 9075904Abstract: A method of determining vulnerability of a cache memory includes associating a first counter with a cache element and periodically incrementing the first counter. When a read or other access that consumes the data in the cache element occurs, a current value of the first counter is accumulated. When a write or other cache access that modifies data in the cache element occurs, the first counter is reset. At the end of an evaluation period, the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable. Dividing this value by the number of clock cycles approximates the vulnerability of this cache element. The vulnerability for a subset of all cache elements may be measured and extrapolated to obtain an estimate for the vulnerability of the cache memory as a whole.Type: GrantFiled: March 13, 2013Date of Patent: July 7, 2015Assignee: Intel CorporationInventors: Javier Carretero Casado, Xavier Vera, Tanausu Ramirez, Daniel Sanchez, Enric Herrero Abellanas, Nicholas Axelos
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Patent number: 9071281Abstract: Embodiments of apparatuses, methods, and storage medium associated with selectively providing error correction to memory are disclosed herein. In one instance, an apparatus may include a memory controller configured to control access to a non-volatile memory having storage locations. The controller may be configured to provide a first error correction arrangement to provide a first level of error correction capability for data stored in the non-volatile memory. The memory controller may include a control/error correction block configured to provide a second error correction arrangement with a second level of error correction capability for data stored in the non-volatile memory. The second level of error correction capability enables correction of at least one bit error more than the first level. The memory controller may be configured to selectively employ the second error correction arrangement to complement the first error correction arrangement. Other embodiments may be described and claimed.Type: GrantFiled: March 10, 2013Date of Patent: June 30, 2015Assignee: Intel CorporationInventors: Javier Carretero Casado, Xavier Vera, Daniel Sanchez, Tanausu Ramirez, Enric Herrero Abellanas, Nicholas Axelos
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Patent number: 9043659Abstract: In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed.Type: GrantFiled: December 28, 2012Date of Patent: May 26, 2015Assignee: Intel CorporationInventors: Enric Herrero Abellanas, Xavier Vera, Javier Carretero Casado, Tanausu Ramirez, Nicholas Axelos, Daniel Sanchez
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Publication number: 20140281740Abstract: A method of determining vulnerability of a cache memory includes associating a first counter with a cache element and periodically incrementing the first counter. When a read or other access that consumes the data in the cache element occurs, a current value of the first counter is accumulated. When a write or other cache access that modifies data in the cache element occurs, the first counter is reset. At the end of an evaluation period, the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable. Dividing this value by the number of clock cycles approximates the vulnerability of this cache element. The vulnerability for a subset of all cache elements may be measured and extrapolated to obtain an estimate for the vulnerability of the cache memory as a whole.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: Intel CorporationInventors: Javier Carretero Casado, Xavier Vera, Tanausu Ramirez, Daniel Sanchez, Enric Herrero Abellanas, Nicholas Axelos
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Publication number: 20140281261Abstract: A system, processor and method to reduce the overall detectable unrecoverable FIT rate of a cache by reducing the residency time of dirty lines in a cache. This is accomplished through selectively choosing different replacement policies during execution based on the DUE FIT target of the system. System performance and power is minimally affected while effectively reducing the DUE FIT rate.Type: ApplicationFiled: March 16, 2013Publication date: September 18, 2014Applicant: Intel CorporationInventors: Xavier Vera, Javier Carretero Casado, Enric Herrero Abellanas, Daniel Sanchez, Nicholas Axelos, Tanausu Ramirez