Patents by Inventor Tang HU
Tang HU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972504Abstract: Disclosed a method and a system for overlapping sliding window segmentation of an image based on an FPGA. According to the method, on-chip BRAMs storage resource cost of FPGA is determined; each on-chip BRAM in FPGA is used to cache the pixel data of each segmented sub-image in parallel; when the pixel data received by the BRAMs reaches a preset threshold or the last pixel of the segmented sub-image is written into the on-chip BRAMs, the data is written from the on-chip BRAMs to an off-chip DDR memory in a burst continuous writing mode; the repeated data generated by segmentation of horizontally overlapping sliding windows are written into the on-chip BRAMs corresponding to the current segmented sub-image and adjacent segmented sub-images thereof respectively in a synchronous and parallel manner.Type: GrantFiled: May 26, 2023Date of Patent: April 30, 2024Assignee: ZHEJIANG LABInventors: Tang Hu, Xiao Yu, Xiangdi Li, Songnan Ren, Li Yan
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Publication number: 20240054597Abstract: Disclosed a method and a system for overlapping sliding window segmentation of an image based on an FPGA. According to the method, on-chip BRAMs storage resource cost of FPGA is determined; each on-chip BRAM in FPGA is used to cache the pixel data of each segmented sub-image in parallel; when the pixel data received by the BRAMs reaches a preset threshold or the last pixel of the segmented sub-image is written into the on-chip BRAMs, the data is written from the on-chip BRAMs to an off-chip DDR memory in a burst continuous writing mode; the repeated data generated by segmentation of horizontally overlapping sliding windows are written into the on-chip BRAMs corresponding to the current segmented sub-image and adjacent segmented sub-images thereof respectively in a synchronous and parallel manner.Type: ApplicationFiled: May 26, 2023Publication date: February 15, 2024Inventors: Tang HU, Xiao YU, Xiangdi LI, Songnan REN, Li YAN
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Patent number: 11209705Abstract: A display panel has an odd-shaped active area and a peripheral area. The display panel includes a substrate, pixel units, gate lines and at least one dummy thin film transistor. The pixel units are disposed on the active area of the substrate. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units a second gate line coupled to of the gate lines. The dummy thin film transistor is disposed on the substrate, and is coupled to the first gate line.Type: GrantFiled: June 4, 2019Date of Patent: December 28, 2021Assignee: HannStar Display CorporationInventors: Chia-Hua Yu, Sung-Chun Lin, Hsien-Tang Hu, Hsuan-Chen Liu, Chien-Ting Chan
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Patent number: 11092859Abstract: The present invention provides a display panel, the display panel includes at least one first inner sub-pixel disposed in a display region of the display panel and a plurality of first compensation sub-pixels disposed between an end of the first sub-pixel column and the first inner sub-pixel, and a shape of the display region is non-rectangular. Each of the first inner sub-pixel and the first compensation sub-pixels includes a sub-pixel unit, a light shielding sub-block and a color filter block, structures of the sub-pixel units of the first compensation sub-pixels are different from a structure of the sub-pixel unit of the first inner sub-pixel, and the structures of the sub-pixel units of the first compensation sub-pixels are different from each other.Type: GrantFiled: May 7, 2020Date of Patent: August 17, 2021Assignee: HANNSTAR DISPLAY CORPORATIONInventors: Chung-Lin Chang, Hsien-Tang Hu, Kun-Tsai Huang
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Patent number: 10885822Abstract: A gate driving circuit and a display panel with the gate driving circuit are provided. The gate driving circuit includes shift registers for providing scan signals to gate lines of the display panel. Each shift register includes a main circuit and a discharge circuit. In the main circuit, a pre-charge unit is coupled to a first node and is configured to output a pre-charge signal to the first node, a pull-up unit is coupled to the first node and a second node and is configured to output an mth stage scan signal of the 1st to Nth stage scan signals to the second node; and a reset unit is coupled to the first node and is configured to receive a reset signal. In the discharge circuit, a pull-down unit is coupled to the first node and the second node and is configured to receive a pull-down control signal.Type: GrantFiled: April 29, 2019Date of Patent: January 5, 2021Assignee: HannStar Display CorporationInventors: Hsien-Tang Hu, Hsuan-Chen Liu, Chien-Ting Chan
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Publication number: 20200365102Abstract: The present invention provides a display panel, the display panel includes at least one first inner sub-pixel disposed in a display region of the display panel and a plurality of first compensation sub-pixels disposed between an end of the first sub-pixel column and the first inner sub-pixel, and a shape of the display region is non-rectangular. Each of the first inner sub-pixel and the first compensation sub-pixels includes a sub-pixel unit, a light shielding sub-block and a color filter block, structures of the sub-pixel units of the first compensation sub-pixels are different from a structure of the sub-pixel unit of the first inner sub-pixel, and the structures of the sub-pixel units of the first compensation sub-pixels are different from each other.Type: ApplicationFiled: May 7, 2020Publication date: November 19, 2020Inventors: Chung-Lin Chang, Hsien-Tang Hu, Kun-Tsai Huang
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Patent number: 10783840Abstract: A display panel including a first substrate, a second substrate opposite to the first substrate, and a display medium located between the first substrate and the second substrate is provided. The display panel further includes a plurality of pixel structures, a plurality of data lines and a plurality of scan lines electrically connected to the pixel structures, a first driving unit located at a peripheral area, at least one test line, and at least one first pad located at the peripheral area. Each of the data lines has a first end and a second end opposite to each other. The first driving unit is electrically connected to the first ends of the data lines. The at least one test line is electrically connected to the second ends of at least part of the data lines. The at least one test line is grounded through the at least one first pad.Type: GrantFiled: August 28, 2018Date of Patent: September 22, 2020Assignee: HannStar Display CorporationInventors: Sung-Chun Lin, Hsien-Tang Hu, Hsuan-Chen Liu, Chien-Ting Chan
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Patent number: 10700020Abstract: A thin film transistor substrate having a display region and a peripheral region, and the thin film transistor substrate includes a first substrate, scan lines, data lines, an insulating layer, first thin film transistors, at least one passivation layer and at least one gate driving circuit. The first substrate has an electrostatic protection area and a driving circuit area, and the electrostatic protection area and the driving circuit area are situated in the peripheral region. The scan lines, the data lines and the first thin film transistors are disposed in the display region. The insulating layer includes a gate insulator of the first thin film transistor, and the passivation layer is disposed on the insulating layer. The gate driving circuit is disposed in the driving circuit area. At least one of the passivation layer and the insulating layer are not disposed in the electrostatic protection area.Type: GrantFiled: February 25, 2018Date of Patent: June 30, 2020Assignee: HANNSTAR DISPLAY CORPORATIONInventors: Sung-Chun Lin, Hsien-Tang Hu, Hsuan-Chen Liu, Chien-Ting Chan
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Patent number: 10643522Abstract: In a shift register, a pre-charge unit is configured to receive a first input signal and output a pre-charge signal to a first node, a pull-up unit is configured to output a scan signal to a second node, and a pull-down unit is configured to receive a pull-down control signal. The pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status.Type: GrantFiled: August 20, 2018Date of Patent: May 5, 2020Assignee: HannStar Display CorporationInventors: Hsien-Tang Hu, Hsuan-Chen Liu, Chien-Ting Chan
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Publication number: 20190377234Abstract: A display panel has an odd-shaped active area and a peripheral area. The display panel includes a substrate, pixel units, gate lines and at least one dummy thin film transistor. The pixel units are disposed on the active area of the substrate. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of pixel units coupled to a first gate line of the gate lines is smaller than the number of pixel units a second gate line coupled to of the gate lines. The dummy thin film transistor is disposed on the substrate, and is coupled to the first gate line.Type: ApplicationFiled: June 4, 2019Publication date: December 12, 2019Inventors: Chia-Hua YU, Sung-Chun LIN, Hsien-Tang HU, Hsuan-Chen LIU, Chien-Ting CHAN
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Publication number: 20190340969Abstract: A gate driving circuit and a display panel with the gate driving circuit are provided. The gate driving circuit includes shift registers for providing scan signals to gate lines of the display panel. Each shift register includes a main circuit and a discharge circuit. In the main circuit, a pre-charge unit is coupled to a first node and is configured to output a pre-charge signal to the first node, a pull-up unit is coupled to the first node and a second node and is configured to output an mth stage scan signal of the 1st to Nth stage scan signals to the second node; and a reset unit is coupled to the first node and is configured to receive a reset signal. In the discharge circuit, a pull-down unit is coupled to the first node and the second node and is configured to receive a pull-down control signal.Type: ApplicationFiled: April 29, 2019Publication date: November 7, 2019Inventors: Hsien-Tang HU, Hsuan-Chen LIU, Chien-Ting CHAN
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Patent number: 10469088Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.Type: GrantFiled: February 21, 2019Date of Patent: November 5, 2019Assignee: Ambarella, Inc.Inventors: Tu-I Tsai, David Chiong, Dennis He, Chien-Tang Hu
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Patent number: 10403382Abstract: The invention provides a gate driving circuit and a display apparatus. The gate driving circuit includes 1st to Nth stage shift registers for respectively generating and sequentially outputting 1st to Nth stage scan signals to the display panel, where N is an integer greater than or equal to 4. Each of the shift registers is configured to receive a starting signal, and the starting signal is utilized to trigger the 1st and 2nd stage shift registers to generate the 1st and 2nd stage scan signals respectively, and the starting signal is utilized to reset the 3rd to Nth stage shift registers.Type: GrantFiled: November 15, 2016Date of Patent: September 3, 2019Assignee: HannStar Display CorporationInventors: Sung-Chun Lin, Chien-Ting Chan, Yu-Tuan Hsu, Po-Yi Chen, Hsien-Tang Hu, Hsuan-Chen Liu
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Publication number: 20190139501Abstract: A display panel including a first substrate, a second substrate opposite to the first substrate, and a display medium located between the first substrate and the second substrate is provided. The display panel further includes a plurality of pixel structures, a plurality of data lines and a plurality of scan lines electrically connected to the pixel structures, a first driving unit located at a peripheral area, at least one test line, and at least one first pad located at the peripheral area. Each of the data lines has a first end and a second end opposite to each other. The first driving unit is electrically connected to the first ends of the data lines. The at least one test line is electrically connected to the second ends of at least part of the data lines. The at least one test line is grounded through the at least one first pad.Type: ApplicationFiled: August 28, 2018Publication date: May 9, 2019Applicant: HannStar Display CorporationInventors: Sung-Chun Lin, Hsien-Tang Hu, Hsuan-Chen Liu, Chien-Ting Chan
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Patent number: 10254612Abstract: A display panel is provided, and includes a first substrate, a connecting structure, a passivation layer, a second substrate and a sealant. The first substrate has an active area and a peripheral area. The connecting structure is disposed on the first substrate and located in the peripheral area, and is configured to electrically connect different metal layers. The passivation layer is disposed on and covers the connecting structure. The second substrate is disposed opposite to the first substrate. The sealant is sandwiched between the first substrate and the second substrate. In the display panel, a vertical projection of the sealant on the first substrate and a vertical projection of the connecting structure on the first substrate are overlapped.Type: GrantFiled: June 15, 2017Date of Patent: April 9, 2019Assignees: HannStar Display (Nanjing) Corporation, HannStar Display CorporationInventors: Hsien-Tang Hu, Hsuan-Chen Liu, Chien-Ting Chan
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Patent number: 10236889Abstract: An apparatus includes a fractional divider and a modulator circuit. The fractional divider circuit may be configured to generate a feedback clock signal in response to a selection signal, a divided clock signal and an output clock signal. The modulator circuit may be configured to generate the selection signal in response to the feedback clock signal. The fractional divider may generate four phase clock signals from the divided clock signal. The four phase clock signals may be interleaved by the fractional divider circuit to select one of the four phase clock signals as the feedback clock signal. The fractional divider operates at a divide-by-4 clock speed. The selection signal may be synchronized in response to the divided clock signal to generate the feedback clock signal. The fractional divider circuit may be implemented using CMOS logic.Type: GrantFiled: February 17, 2018Date of Patent: March 19, 2019Assignee: Ambarella, Inc.Inventors: Tu-I Tsai, David Chiong, Dennis He, Chien-Tang Hu
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Publication number: 20190073939Abstract: In a shift register, a pre-charge unit is configured to receive a first input signal and output a pre-charge signal to a first node, a pull-up unit is configured to output a scan signal to a second node, and a pull-down unit is configured to receive a pull-down control signal. The pull-down control signal switches from a disable voltage to an enable voltage before the display panel switches from a non-display status to a display status.Type: ApplicationFiled: August 20, 2018Publication date: March 7, 2019Inventors: Hsien-Tang HU, Hsuan-Chen LIU, Chien-Ting CHAN
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Publication number: 20190067218Abstract: A thin film transistor substrate having a display region and a peripheral region, and the thin film transistor substrate includes a first substrate, scan lines, data lines, an insulating layer, first thin film transistors, at least one passivation layer and at least one gate driving circuit. The first substrate has an electrostatic protection area and a driving circuit area, and the electrostatic protection area and the driving circuit area are situated in the peripheral region. The scan lines, the data lines and the first thin film transistors are disposed in the display region. The insulating layer includes a gate insulator of the first thin film transistor, and the passivation layer is disposed on the insulating layer. The gate driving circuit is disposed in the driving circuit area. At least one of the passivation layer and the insulating layer are not disposed in the electrostatic protection area.Type: ApplicationFiled: February 25, 2018Publication date: February 28, 2019Inventors: Sung-Chun Lin, Hsien-Tang Hu, Hsuan-Chen Liu, Chien-Ting Chan
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Publication number: 20180188574Abstract: A display panel is provided, and includes a first substrate, a connecting structure, a passivation layer, a second substrate and a sealant. The first substrate has an active area and a peripheral area. The connecting structure is disposed on the first substrate and located in the peripheral area, and is configured to electrically connect different metal layers, The passivation layer is disposed on and covers the connecting structure. The second substrate is disposed opposite to the first substrate. The sealant is sandwiched between the first substrate and the second substrate. In the display panel, a vertical projection of the sealant on the first substrate and a vertical projection of the connecting structure on the first substrate are overlapped.Type: ApplicationFiled: June 15, 2017Publication date: July 5, 2018Inventors: Hsien-Tang HU, Hsuan-Chen LIU, Chien-Ting CHAN
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Publication number: 20180040272Abstract: The invention provides a gate driving circuit and a display apparatus. The gate driving circuit includes 1st to Nth stage shift registers for respectively generating and sequentially outputting 1st to Nth stage scan signals to the display panel, where N is an integer greater than or equal to 4. Each of the shift registers is configured to receive a starting signal, and the starting signal is utilized to trigger the 1st and 2nd stage shift registers to generate the 1st and 2nd stage scan signals respectively, and the starting signal is utilized to reset the 3rd to Nth stage shift registers.Type: ApplicationFiled: November 15, 2016Publication date: February 8, 2018Inventors: Sung-Chun LIN, Chien-Ting CHAN, Yu-Tuan HSU, Po-Yi CHEN, Hsien-Tang HU, Hsuan-Chen LIU