Abstract: A method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one photomask for creating vias and trenches is needed instead of the conventional two masks. The function of the second mask is replaced by a series of plasma etch steps, which exploit differential etch rates for areas which are open relative to areas which are narrow and constricted. As a technical advantage of the invention, each interconnection created by the method of the invention is a structure of wider trenches and narrower vias, wherein the diameter of the vias is approximately the same as the narrowest width of the reverse trench pattern, and each via is centered within the trench. The reverse trench pattern surrounding the via is approximately twice the width of the via diameter.

Abstract: The electroplating of copper is the leading technology for forming copper lines on integrated circuits. In the copper electroplating process a negative potential is applied to the semiconductor wafer with the surface of the semiconductor wafer acting as the cathode. The anode will be partially or wholly formed with copper. Both the anode and the semiconductor will be exposed to a solution comprising copper electrolytes. By reducing the temperature of the copper electrolytes solution below 25° C. the rate of self annealing grain growth will increase reducing the final resistively of the copper lines.

Abstract: A method for fabricating circuit interconnects in integrated circuits comprising vertical vias and horizontal trenches between metal lines, wherein only one photomask for creating vias and trenches is needed instead of the conventional two masks. The function of the second mask is replaced by a series of plasma etch steps, which exploit differential etch rates for areas which are open relative to areas which are narrow and constricted.

Abstract: A method for completing an integrated circuit in the horizontal surface of a semiconductor substrate having interconnecting metal lines, comprising the steps of forming a dielectric layer over a said substrate; etching a substantially vertical hole into said dielectric layer so that it exposes one of said metal lines; depositing a barrier layer over said structure including within said hole, said barrier layer operable to seal said dielectric sidewalls of said structure; selectively removing said barrier layer from the bottom of said hole, thereby exposing said metal line; and forming a copper interconnect structure in said structure, contacting said metal line.

Abstract: A method of fabricating an integrated circuit. A thin liner (110, 210, 310) is deposited over dielectric layer including within a trench (108) and/or via (106). The thin liner (110, 210, 310) smoothes the sidewalls of the trench (108) and/or via (106) and reduces resistivity. The thin liner may comprise an organic or inorganic dielectric (110) or metal (210,310). A copper interconnect structure (116, 216, 316) is then formed over the thin liner (110, 210, 310).

Abstract: A copper interconnect having a barrier layer (106, 206). A metal barrier layer may be co-deposited with Si to form barrier (106) or a metal barrier layer may be deposited followed by surface treatment with a Si-containing ambient to form barrier (206). The copper (110) is then deposited over the said barrier layer (106,206) with good adhesion.

Abstract: A copper interconnect having a transition metal-silicon-nitride barrier (106). A transition metal-nitride is co-deposited with Si by reactive sputtering in a Si containing ambient to form barrier (106). The copper (110) is then deposited over the transition metal-silicon-nitride barrier (108) with good adhesion.

Abstract: The present invention describes a method for testing the interconnect networks of a multichip module for opens and shorts. An electron beam lands on a pad of an interconnect network located on a substrate. The electron beam is used to interrogate the pad. An extract grid located above the substrate is maintained at a positive potential. While the electron beam interrogates the pad, the pad emits secondary electrons until such a point that the pad reaches a positive potential near that of the positive potential of the extract grid. The extract grid is then switched to a negative potential. The pad, still being interrogated by the electron beam, then collects secondary electrons until such a point that the pad reaches a negative potential near that of the negative potential of the extract grid. The test time, the length of time it takes for the pad to change from the positive potential to the negative potential, is measured and compared to a reference value.