Patents by Inventor Tang-Xuan Zhong
Tang-Xuan Zhong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11355642Abstract: Methods for manufacturing semiconductor structures are provided. The method includes forming a first masking layer over a substrate and forming a second masking layer over the first masking layer. The method includes forming a photoresist pattern over the second masking layer and patterning the second masking layer through the photoresist pattern. The method further includes diminishing the photoresist pattern and patterning the second masking layer and the first masking layer through the diminished photoresist pattern. The method further includes removing the diminished photoresist pattern and patterning the semiconductor substrate through the second masking layer and the first masking layer to form a fin structure. The method further includes forming a gate structure over the fin structure.Type: GrantFiled: October 18, 2019Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
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Publication number: 20200052122Abstract: Methods for manufacturing semiconductor structures are provided. The method includes forming a first masking layer over a substrate and forming a second masking layer over the first masking layer. The method includes forming a photoresist pattern over the second masking layer and patterning the second masking layer through the photoresist pattern. The method further includes diminishing the photoresist pattern and patterning the second masking layer and the first masking layer through the diminished photoresist pattern. The method further includes removing the diminished photoresist pattern and patterning the semiconductor substrate through the second masking layer and the first masking layer to form a fin structure. The method further includes forming a gate structure over the fin structure.Type: ApplicationFiled: October 18, 2019Publication date: February 13, 2020Inventors: Ju-Wang HSU, Chih-Yuan TING, Tang-Xuan ZHONG, Yi-Nien SU, Jang-Shiang TSAI
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Patent number: 10483397Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.Type: GrantFiled: December 24, 2014Date of Patent: November 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
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Publication number: 20150137265Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.Type: ApplicationFiled: December 24, 2014Publication date: May 21, 2015Inventors: Ju-Wang HSU, Chih-Yuan TING, Tang-Xuan ZHONG, Yi-Nien SU, Jang-Shiang TSAI
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Patent number: 8927353Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.Type: GrantFiled: May 7, 2007Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
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Patent number: 7511988Abstract: A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.Type: GrantFiled: July 10, 2006Date of Patent: March 31, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wesley Lin, Fang-Shi Jordan Lai, Chia-Fu Lee, Sheng Chi Lin, Ping-Wei Wang, Chang-Yun Chang, Tang-Xuan Zhong, Tsung-Lin Lee
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Publication number: 20080277745Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor comprises a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further comprises shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further comprises a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.Type: ApplicationFiled: May 7, 2007Publication date: November 13, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
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Patent number: 7381649Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: GrantFiled: July 29, 2005Date of Patent: June 3, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
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Publication number: 20070268747Abstract: A static random access memory (SRAM) cell includes a first load device, a first pull-down transistor, and a switch-box coupled between the first load device and the first pull-down transistor. The switch-box is configured to receive a switch control signal to turn off a first connection between the first load device and the first pull-down transistor during read operations of the SRAM cell and to turn on the first connection during write operations.Type: ApplicationFiled: July 10, 2006Publication date: November 22, 2007Inventors: Wesley Lin, Fang-Shi Jordan Lai, Chia-Fu Lee, Sheng Chi Lin, Ping-Wei Wang, Chang-Yun Chang, Tang-Xuan Zhong, Tsung-Lin Lee
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Patent number: 7265425Abstract: A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.Type: GrantFiled: November 15, 2004Date of Patent: September 4, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Hsin Chen, Tang-Xuan Zhong, Chien-Chao Huang, Cheng-Kuo Wen, Di-Hong Lee
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Publication number: 20070026629Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: ApplicationFiled: July 29, 2005Publication date: February 1, 2007Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu
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Publication number: 20060102955Abstract: A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.Type: ApplicationFiled: November 15, 2004Publication date: May 18, 2006Inventors: Kuang-Hsin Chen, Tang-Xuan Zhong, Chien-Chao Huang, Cheng-Kuo Wen, Di-Hong Lee
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Patent number: RE45165Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: GrantFiled: February 14, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yu Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
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Patent number: RE45180Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: GrantFiled: June 2, 2010Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang