Abstract: A device includes a first AND logic gate comprising a first input, a second input, and an output, a second AND logic gate comprising a first input, a second input, and an output, and a first OR logic gate comprising a first input coupled to the output of the first AND logic gate and a second input coupled to the output of the second AND logic gate. A first selection circuit has first and second data inputs, a first control input coupled to the first input of the first AND logic gate and a second control input coupled to the first input of the second AND logic gate. A first D latch includes a data input coupled to an output of the first selection circuit and an activation input coupled to an output of the first OR logic gate and a second D latch includes a data input coupled to the output of the first selection circuit and an activation input coupled to the output of the first OR logic gate.

Abstract: A method includes receiving a selection signal from a third-party device and a status signal from the third-party device. A data signal from the third-party device is latched when both the selection signal and the status signal are active. In addition, a second selection signal and a second status signal can be received from a second third-party device and a second data signal latched when both the second selection signal and the second status signal are active.

Abstract: A method includes receiving a selection signal from a third-party device and a status signal from the third-party device. A data signal from the third-party device is latched when both the selection signal and the status signal are active. In addition, a second selection signal and a second status signal can be received from a second third-party device and a second data signal latched when both the second selection signal and the second status signal are active.

Abstract: A device includes an AND logic gate and a D latch. The AND logic gate includes a first input configured to be coupled to a third-party device to receive a selection signal, a second input configured to be coupled to the third-party device to receive a status signal, and an output configured to transmit an output signal when the selection signal and the status signal are received. The D latch is capable of storing datum. The D latch includes an activation input coupled to the output of the AND logic gate and a data input configured to be coupled to the third-party device to receive a data signal that is representative of the datum. The D latch is configured to store the datum in response to the output signal.