Abstract: A storage device comprises a controller, such as an ASIC controller, and one or more NAND flash memory devices. The controller comprises a differential receiver and a delay locked loop circuit. During read and write operations, the controller is configured to vary a delay of a data strobe signal by an interval across a width of a data window using the delay locked loop circuit, and to compare a write pattern to a read pattern for each delayed interval to determine the timing margins of the storage device. During read and write operations, the controller is further configured to apply a reference voltage to a host interface or a memory interface, increment and decrement the reference voltage by a set value, and compare a write pattern to a read pattern for each varied reference voltage value to determine the voltage margins of the storage device.

Abstract: A storage device comprises a controller, such as an ASIC controller, and one or more NAND flash memory devices. The controller comprises a differential receiver and a delay locked loop circuit. During read and write operations, the controller is configured to vary a delay of a data strobe signal by an interval across a width of a data window using the delay locked loop circuit, and to compare a write pattern to a read pattern for each delayed interval to determine the timing margins of the storage device. During read and write operations, the controller is further configured to apply a reference voltage to a host interface or a memory interface, increment and decrement the reference voltage by a set value, and compare a write pattern to a read pattern for each varied reference voltage value to determine the voltage margins of the storage device.