Patents by Inventor Tanja Braun

Tanja Braun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11328987
    Abstract: A wafer-level packaging based module includes an antenna board and a chip board. The antenna board includes at least one antenna layer with introduced antenna element and a shielding layer with introduced shielding element in the area of the at least one antenna element opposite to the antenna layer. The chip board includes a contacting layer, a rewiring layer opposite to the contacting layer and the shielding layer having at least one shielding element arranged on the rewiring layer. A chip layer having at least one chip is arranged between the contacting layer and the rewiring layer. Further, the chip layer includes at least one via connecting the contacting layer to the rewiring layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 10, 2022
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun, Klaus-Dieter Lang
  • Patent number: 10978778
    Abstract: A wafer level package with integrated antenna includes a contacting layer, an antenna layer with integrated antenna as well as a chip layer having at least one chip arranged between the contacting layer and the antenna layer. Further, means for shielding are implemented between the antenna layer and the chip layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: April 13, 2021
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun
  • Patent number: 10797375
    Abstract: A wafer level package with at least one integrated antenna element includes a chip layer with at least one chip, a dielectric layer as well as an antenna layer arranged between the chip layer and the dielectric layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 6, 2020
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun
  • Publication number: 20200176376
    Abstract: A wafer-level packaging based module includes an antenna board and a chip board. The antenna board includes at least one antenna layer with introduced antenna element and a shielding layer with introduced shielding element in the area of the at least one antenna element opposite to the antenna layer. The chip board includes a contacting layer, a rewiring layer opposite to the contacting layer and the shielding layer having at least one shielding element arranged on the rewiring layer. A chip layer having at least one chip is arranged between the contacting layer and the rewiring layer. Further, the chip layer includes at least one via connecting the contacting layer to the rewiring layer.
    Type: Application
    Filed: November 26, 2019
    Publication date: June 4, 2020
    Inventors: Ivan NDIP, Tanja BRAUN, Klaus-Dieter LANG
  • Patent number: 10461399
    Abstract: A wafer level package with integrated antenna includes a contacting layer, a redistribution layer as well as a chip layer arranged between the contacting layer and the redistribution layer. An antenna is integrated in the redistribution layer. The antenna is shielded from the chip by means of a via, offset and provided with a reflector. Alternatively, the antenna can also be provided as antenna element in the chip layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: October 29, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun
  • Patent number: 10424827
    Abstract: A wafer level package with integrated antenna includes a contacting layer, a redistribution layer as well as a chip layer arranged between the contacting layer and the redistribution layer. An antenna is integrated in the redistribution layer. The antenna is shielded from the chip by means of a via, offset and provided with a reflector. Alternatively, the antenna can also be provided as antenna element in the chip layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: September 24, 2019
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun
  • Patent number: 10403576
    Abstract: A method for manufacturing an electronic component can include the following steps: providing a semiconductor arrangement comprising a carrier structure which has at least one semiconductor chip incorporated into a potting compound, and a redistribution layer which comprises a flexible material and at least one strip conductor, wherein the carrier structure at least in regions is connected to the redistribution layer, and the at least one semiconductor chip is electrically conductively connected to the redistribution layer, and separating the carrier structure along at least one trench in a manner such that the carrier structure is divided into at least two singularized carrier elements, wherein two adjacent ones of the singularized carrier elements are connected to one another over the respective trench by way of the redistribution layer.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: September 3, 2019
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Tanja Braun, Karl-Friedrich Becker, Ruben Kahle, Michael Töpper
  • Publication number: 20180191051
    Abstract: A wafer level package with at least one integrated antenna element includes a chip layer with at least one chip, a dielectric layer as well as an antenna layer arranged between the chip layer and the dielectric layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 5, 2018
    Inventors: Ivan NDIP, Tanja Braun
  • Publication number: 20180191052
    Abstract: A wafer level package with integrated antenna includes a contacting layer, an antenna layer with integrated antenna as well as a chip layer having at least one chip arranged between the contacting layer and the antenna layer. Further, means for shielding are implemented between the antenna layer and the chip layer.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 5, 2018
    Inventors: Ivan NDIP, Tanja BRAUN
  • Publication number: 20180191053
    Abstract: A wafer level package with integrated antenna includes a contacting layer, a redistribution layer as well as a chip layer arranged between the contacting layer and the redistribution layer. An antenna is integrated in the redistribution layer. The antenna is shielded from the chip by means of a via, offset and provided with a reflector. Alternatively, the antenna can also be provided as antenna element in the chip layer.
    Type: Application
    Filed: January 3, 2018
    Publication date: July 5, 2018
    Inventors: Ivan NDIP, Tanja BRAUN
  • Publication number: 20170098611
    Abstract: A method for manufacturing an electronic component can include the following steps: providing a semiconductor arrangement comprising a carrier structure which has at least one semiconductor chip incorporated into a potting compound, and a redistribution layer which comprises a flexible material and at least one strip conductor, wherein the carrier structure at least in regions is connected to the redistribution layer, and the at least one semiconductor chip is electrically conductively connected to the redistribution layer, and separating the carrier structure along at least one trench in a manner such that the carrier structure is divided into at least two singularized carrier elements, wherein two adjacent ones of the singularized carrier elements are connected to one another over the respective trench by way of the redistribution layer.
    Type: Application
    Filed: October 4, 2016
    Publication date: April 6, 2017
    Inventors: Tanja Braun, Karl-Friedrich Becker, Ruben Kahle, Michael Töpper
  • Patent number: 7011989
    Abstract: A method for producing encapsulated chips includes preparing a wafer with contacts projecting from a surface of the wafer. The wafer is disposed on a dicing substrate and diced into a plurality of spaced chips on the dicing substrate. The contacts are covered with a protection arrangement, then injection molding being conducted to introduce encapsulation material into the contacts and the trenches. Then the protection arrangement is removed so that the contacts are exposed.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: March 14, 2006
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.
    Inventors: Karl-Friedrich Becker, Tanja Braun, Mathias Koch, Andreas Ostmann, Lars Böttcher, Erik Jung
  • Publication number: 20040110323
    Abstract: A method for producing encapsulated chips includes preparing a wafer with contacts projecting from a surface of the wafer. The wafer is disposed on a dicing substrate and diced into a plurality of spaced chips on the dicing substrate. The contacts are covered with a protection arrangement, then injection molding being conducted to introduce encapsulation material into the contacts and the trenches. Then the protection arrangement is removed so that the contacts are exposed.
    Type: Application
    Filed: October 30, 2003
    Publication date: June 10, 2004
    Inventors: Karl-Friedrich Becker, Tanja Braun, Mathias Koch, Andreas Ostmann, Lars Bottcher, Erik Jung