Abstract: A calculating unit including a number of bit slices which is less than the number of positions of the operand to be processed. Each bit slice has a logic element and a communication bus between the logic element and the plurality of register cells. The register cells are connected in parallel with respect to the slice-internal communication bus and are controlled by a controller so that only one register cell of the plurality of register cells is coupled to the communication bus at a time.

Abstract: An XOR circuit designed in dual rail includes four shunt transistors, wherein the shunt transistors are disposed to couple an input potential at a first input or a second input with an output.

Abstract: The calculating unit includes a dual rail input stage, a switching stage for a bit to be calculated and an output stage for an output bit, wherein the output stage provides a dual rail output. The switching stage is not implemented in dual rail technology but according to a “one-hot” realization. The switching stage includes at least one internal node which is, in the preparation mode according to a control signal on a control line from a control means, connected to a reference potential, while the node potential circuit for handling the internal node in the data mode is not active. Thus, an area-efficient, cross-current-reduced and reliable calculating unit is obtained, which may additionally be clocked at high speed, as a transition form a preparation mode to a data mode takes place without time-consuming discharge processes.

Abstract: The calculating unit includes a dual rail input stage, a switching stage for a bit to be calculated and an output stage for an output bit, wherein the output stage provides a dual rail output. The switching stage is not implemented in dual rail technology but according to a “one-hot” realization. The switching stage includes at least one internal node which is, in the preparation mode according to a control signal on a control line from a control means, connected to a reference potential, while the node potential circuit for handling the internal node in the data mode is not active. Thus, an area-efficient, cross-current-reduced and reliable calculating unit is obtained, which may additionally be clocked at high speed, as a transition form a preparation mode to a data mode takes place without time-consuming discharge processes.

Abstract: An XOR circuit designed in dual rail includes four shunt transistors, wherein the shunt transistors are disposed to couple an input potential at a first input or a second input with an output.

Abstract: A register cell includes a first input for a data unit to be written into the register cell. The register cell includes further a second input for a negated data unit to be written into the register cell. A first pair of oppositely coupled inverters as a first storage circuit is adapted to be coupled to the first input. A second pair of oppositely coupled inverters as a second storage circuit is adapted to be coupled to a second input. Using two oppositely coupled pairs of inverters makes it possible to initialize both the first input and the second input of the register either to a high voltage state (precharge) or to a low voltage state (discharge), such that the power consumption of the register cell is homogenized from one working clock to the next.

Abstract: A calculating unit including a number of bit slices which is less than the number of positions of the operand to be processed. Each bit slice has a logic element and a communication bus between the logic element and the plurality of register cells. The register cells are connected in parallel with respect to the slice-internal communication bus and are controlled by a controller so that only one register cell of the plurality of register cells is coupled to the communication bus at a time.

Abstract: A register cell includes a first input for a data unit to be written into the register cell. The register cell includes further a second input for a negated data unit to be written into the register cell. A first pair of oppositely coupled inverters as a first storage circuit is adapted to be coupled to the first input. A second pair of oppositely coupled inverters as a second storage circuit is adapted to be coupled to a second input. Using two oppositely coupled pairs of inverters makes it possible to initialize both the first input and the second input of the register either to a high voltage state (precharge) or to a low voltage state (discharge), such that the power consumption of the register cell is homogenized from one working clock to the next.