Abstract: Presented herein are techniques enable existing hardware input/output resources, such as the hardware queues (queue control registers), of a network interface card to be shared with different hosts (i.e., each queue mapped to many hosts) by logically segregating the hardware I/O resources using assignable interfaces each associated with a distinct Process Address Space Identifier (PASID). That is, different assignable interfaces are created and associated with different PASIDs, and these assignable interfaces each correspond to a different host (i.e., there is a mapping between a host, an assignable interface, a PASID, and a partition of a hardware queue). The result is that that the hosts can use the assignable interface to directly access the hardware queue partition that corresponds thereto.

Abstract: The disclosed technology relates to a process for general-purpose ring buffer handling in a network controller. Specifically, general purpose ring buffers are used in software queue on both the host domain and the network controller to carry out user-defined protocols. The protocols define the relationship of the ring buffers in the host domain and the network controller domain (e.g. how data is moved and processed). The protocols minimize interruptions to the network controller. Furthermore, the implementation of ring buffers in the network controller domain also provides additional resources to the host domain for carrying out the user-defined protocols.

Abstract: Presented herein are methodologies for increasing effective throughput on a network. A method includes receiving a command request via a communication bus, the command request including a command ID, determining, based on the command ID, whether data in the command request is to be joined with data from other command requests having the same command ID, when it is determined, based on the command ID, that the data in the command request is to be joined with other data from other command requests having the same command ID, writing the data to a selected buffer in which the other data is already stored, and causing the data and the other data in the buffer to be sent as a payload of a single packet across a communications fabric.

Abstract: In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.

Abstract: In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.

Abstract: Presented herein are techniques enable existing hardware input/output resources, such as the hardware queues (queue control registers), of a network interface card to be shared with different hosts (i.e., each queue mapped to many hosts) by logically segregating the hardware I/O resources using assignable interfaces each associated with a distinct Process Address Space Identifier (PASID). That is, different assignable interfaces are created and associated with different PASIDs, and these assignable interfaces each correspond to a different host (i.e., there is a mapping between a host, an assignable interface, a PASID, and a partition of a hardware queue). The result is that that the hosts can use the assignable interface to directly access the hardware queue partition that corresponds thereto.

Abstract: The disclosed technology relates to a process for general-purpose ring buffer handling in a network controller. Specifically, general purpose ring buffers are used in software queue on both the host domain and the network controller to carry out user-defined protocols. The protocols define the relationship of the ring buffers in the host domain and the network controller domain (e.g. how data is moved and processed). The protocols minimize interruptions to the network controller. Furthermore, the implementation of ring buffers in the network controller domain also provides additional resources to the host domain for carrying out the user-defined protocols.

Abstract: Presented herein are methodologies for increasing effective throughput on a network. A method includes receiving a command request via a communication bus, the command request including a command ID, determining, based on the command ID, whether data in the command request is to be joined with data from other command requests having the same command ID, when it is determined, based on the command ID, that the data in the command request is to be joined with other data from other command requests having the same command ID, writing the data to a selected buffer in which the other data is already stored, and causing the data and the other data in the buffer to be sent as a payload of a single packet across a communications fabric.

Abstract: A method for qualifying random access storage devices is disclosed which includes determining qualification parameters for each of the random access storage devices, determining a configuration for each of the random access storage devices, and qualifying each of the random access storage devices based on the determined qualification parameters and configuration. A tool for qualifying random access storage devices is disclosed which includes a parser for determining qualification parameters, a machine configuration collector for determining random access storage device configuration, and a thread spawner for qualifying each of the random access storage devices based on the determined qualification parameters and configuration.

Abstract: A method for qualifying random access storage devices is disclosed which includes determining qualification parameters for each of the random access storage devices, determining a configuration for each of the random access storage devices, and qualifying each of the random access storage devices based on the determined qualification parameters and configuration. A tool for qualifying random access storage devices is disclosed which includes a parser for determining qualification parameters, a machine configuration collector for determining random access storage device configuration, and a thread spawner for qualifying each of the random access storage devices based on the determined qualification parameters and configuration.