Abstract: In some examples, a circuit includes a first integrator having an input and an output. The circuit also includes a switching architecture having first and second terminals, the first terminal of the switching architecture coupled to the output of the first integrator. The circuit also includes a second integrator having an input and an output, the input of the second integrator coupled to the second terminal of the switching architecture. The circuit also includes a quantizer having an input and an output, the input of the quantizer coupled to the output of the second integrator. The circuit also includes a digital processing circuit having an input and an output, the input of the digital processing circuit coupled to the output of the quantizer.

Abstract: A device includes a loop filter and an integrator. An integrator input couples to a loop filter output. The device includes a quantizer. A quantizer input couples to an integrator output. The device includes a finite impulse response (FIR) filter, with a FIR filter input coupled to a quantizer output, and a FIR filter output coupled to a loop filter input. The device includes first error correction circuitry (FECC), with a FECC input coupled to the quantizer output, and a FECC output coupled to the quantizer input. The FECC includes a first filter having a first number of taps. The device includes second error correction circuitry (SECC), with a SECC input coupled to the quantizer output, and a SECC output coupled to the integrator input. The SECC includes a second filter having a second number of taps greater than the first number of taps.

Abstract: In some examples, a circuit includes a first transistor having a control terminal and first and second terminals. The circuit also includes a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to the control terminal of the first transistor and the second terminal of the first capacitor coupled to the second terminal of the first transistor. The circuit also includes a first switch having first and second terminals, the second terminal of the first switch coupled to the control terminal of the first transistor. The circuit also includes a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to the first terminal of the first transistor and the second terminal of the second capacitor coupled to the first terminal of the first switch.

Abstract: In a described example, a circuit includes a digital-to-analog converter (DAC) unit element switch circuit including first and second sign switch inputs, first and second select switch inputs, and first, second and third DAC outputs. Synchronizer logic includes a selection input and first and second synchronization outputs, in which the first synchronization output is coupled to the first select switch input and the second synchronization output is coupled to the second select switch input. Selection logic includes a data input, a sign control output and a selection control output, in which the sign control output is coupled to the first and second sign switch inputs, and the selection control output is coupled to the selection input.

Abstract: An example apparatus includes: voltage divider circuitry configured to determine a common mode voltage of a differential pair of signals having a first voltage and a second voltage; a first amplifier coupled to the voltage divider circuitry, the first amplifier configured to determine a difference between the common mode voltage and a reference common mode voltage; current compensation circuitry coupled to the first amplifier, the current compensation circuitry configured to generate a first current and a second current responsive to the difference between voltages; and a second amplifier coupled to the voltage divider circuitry and the current compensation circuitry, the second amplifier to compensate the first voltage with the first current and the second voltage with the second current.

Abstract: In a described example, a circuit includes a digital-to-analog converter (DAC) unit element switch circuit including first and second sign switch inputs, first and second select switch inputs, and first, second and third DAC outputs. Synchronizer logic includes a selection input and first and second synchronization outputs, in which the first synchronization output is coupled to the first select switch input and the second synchronization output is coupled to the second select switch input. Selection logic includes a data input, a sign control output and a selection control output, in which the sign control output is coupled to the first and second sign switch inputs, and the selection control output is coupled to the selection input.

Abstract: In some examples, a circuit includes a first integrator having an input and an output. The circuit also includes a switching architecture having first and second terminals, the first terminal of the switching architecture coupled to the output of the first integrator. The circuit also includes a second integrator having an input and an output, the input of the second integrator coupled to the second terminal of the switching architecture. The circuit also includes a quantizer having an input and an output, the input of the quantizer coupled to the output of the second integrator. The circuit also includes a digital processing circuit having an input and an output, the input of the digital processing circuit coupled to the output of the quantizer.

Abstract: In some examples, a circuit includes a first transistor having a control terminal and first and second terminals. The circuit also includes a first capacitor having first and second terminals, the first terminal of the first capacitor coupled to the control terminal of the first transistor and the second terminal of the first capacitor coupled to the second terminal of the first transistor. The circuit also includes a first switch having first and second terminals, the second terminal of the first switch coupled to the control terminal of the first transistor. The circuit also includes a second capacitor having first and second terminals, the first terminal of the second capacitor coupled to the first terminal of the first transistor and the second terminal of the second capacitor coupled to the first terminal of the first switch.

Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

Abstract: A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

Abstract: Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.

Abstract: Systems and methods are disclosed for a signal convertor comprising a resistor or current source coupled to a positive virtual ground node and a negative virtual ground node, wherein the resistor or current source is configured to switch from the positive virtual ground node (VGP) to the negative virtual ground node (VGN), wherein the switching of the resistor or current source results in a shaping of the low frequency noise from the resistor.