Abstract: A method and apparatus for dynamically matching a plurality of resistors to a sensor are disclosed. In the method and apparatus, a switching block of a plurality of switching blocks receives a plurality of selection signals. The switching block is coupled to a resistor array having a plurality of resistors that are coupled in series and arranged in a closed loop. Each two resistors are coupled to each other by a respective resistor node of a plurality of resistor nodes. The switching block of the plurality of switching blocks has a plurality of input nodes and an output node, where the output node is coupled to the respective resistor node of the plurality of resistor nodes. In the method and apparatus, the switching block couples an input node of the plurality of input nodes to the output node based on the selection signals.

Abstract: A method and apparatus for dynamically matching a plurality of resistors to a sensor are disclosed. In the method and apparatus, a switching block of a plurality of switching blocks receives a plurality of selection signals. The switching block is coupled to a resistor array having a plurality of resistors that are coupled in series and arranged in a closed loop. Each two resistors are coupled to each other by a respective resistor node of a plurality of resistor nodes. The switching block of the plurality of switching blocks has a plurality of input nodes and an output node, where the output node is coupled to the respective resistor node of the plurality of resistor nodes. In the method and apparatus, the switching block couples an input node of the plurality of input nodes to the output node based on the selection signals.

Abstract: An apparatus comprising: a sensor; and a resistor array comprising a set of resistors; wherein on a first cycle: at least one first of said resistors is configured to provide a first resistance value; and on a second cycle: at least one second of said resistors is configured to provide said first resistance value.

Abstract: An integrated circuit die includes multiple temperature sensor units each for measuring the temperature of respective regions of a semiconductor substrate of the integrated circuit die. The temperature sensor units are each coupled to a multiplexer by respective groups of signal lines. The signal lines include resistance compensation areas for maintaining a particular ratio of resistances of the signal lines of each group.

Abstract: An integrated circuit die includes multiple temperature sensor units each for measuring the temperature of respective regions of a semiconductor substrate of the integrated circuit die. The temperature sensor units are each coupled to a multiplexer by respective groups of signal lines. The signal lines include resistance compensation areas for maintaining a particular ratio of resistances of the signal lines of each group.

Abstract: An apparatus comprising: a sensor; and a resistor array comprising a set of resistors; wherein on a first cycle: at least one first of said resistors is configured to provide a first resistance value; and on a second cycle: at least one second of said resistors is configured to provide said first resistance value.

Abstract: A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compares the control voltage (voltage input of VCO) with predefined voltage levels during the lock time of the PLL and simultaneously stores the voltage level closest to the control voltage. The stored voltage becomes stable after the PLL has been locked. After power-down is applied and then released, the force control voltage module forces the stored control voltage on the loop filter in a very short time, thereby reducing the re-lock time of the PLL. The loop filter module stabilizes the control voltage. The timer then turns off the force control voltage module by sending a timeout signal after a pre-defined number of clock cycles.

Abstract: A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.

Abstract: A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compares the control voltage (voltage input of VCO) with predefined voltage levels during the lock time of the PLL and simultaneously stores the voltage level closest to the control voltage. The stored voltage becomes stable after the PLL has been locked. After power-down is applied and then released, the force control voltage module forces the stored control voltage on the loop filter in a very short time, thereby reducing the re-lock time of the PLL. The loop filter module stabilizes the control voltage. The timer then turns off the force control voltage module by sending a timeout signal after a pre-defined number of clock cycles.

Abstract: A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.