Patents by Inventor Tanuj Agrawal

Tanuj Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low voltage, master-slave flip-flop
    Patent number: 10637447
    Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 28, 2020
    Inventors: Alok Kumar Tripathi, Amit Verma, Anuj Grover, Deepak Kumar Bihani, Tanmoy Roy, Tanuj Agrawal
  • LOW VOLTAGE, MASTER-SLAVE FLIP-FLOP
    Publication number: 20190273484
    Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 5, 2019
    Inventors: Alok Kumar TRIPATHI, Amit VERMA, Anuj GROVER, Deepak Kumar BIHANI, Tanmoy ROY, Tanuj AGRAWAL
  • Low voltage, master-slave flip-flop
    Patent number: 10277207
    Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 30, 2019
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Alok Kumar Tripathi, Amit Verma, Anuj Grover, Deepak Kumar Bihani, Tanmoy Roy, Tanuj Agrawal