Patents by Inventor Tanuj SAXENA
Tanuj SAXENA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113045Abstract: A semiconductor device has first and second current terminals and a control terminal that can be biased to form an electrically conductive path from the first current terminal to the second current terminal through a channel region is provided with a temperature-sensitive current limiting device. The current-limiting device is integrally formed from semiconductor material of the control terminal and is configured to cause a reduction in electrical current flowing through the channel region when the temperature of the device in the channel region exceeds a predetermined threshold temperature.Type: ApplicationFiled: September 23, 2022Publication date: April 4, 2024Inventors: Tanuj Saxena, John Pigott, Vishnu Khemka, Ljubo Radic, Ganming Qin
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Patent number: 11631763Abstract: A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.Type: GrantFiled: April 4, 2022Date of Patent: April 18, 2023Assignee: NXP USA, Inc.Inventors: Tanuj Saxena, Vishnu Khemka, Bernhard Grote, Ganming Qin, Moaniss Zitouni
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Publication number: 20220393004Abstract: A high voltage trench field plate power MOSFET device is fabricated in a substrate having first and second trenches separated from one another by a narrow epitaxial semiconductor drift pillar structure, where insulated gate electrode layers and insulated field plate layers are formed in the first and second trenches, and where a body well region is formed in an upper portion of the narrow epitaxial semiconductor drift pillar structure to include source contact regions in an active area, and to include an integrated ballast resistor section which connects one or more of the source contact regions to the termination area and which has no source contact regions.Type: ApplicationFiled: May 26, 2022Publication date: December 8, 2022Inventors: Tanuj Saxena, Christian Torrent, Vishnu Khemka, Ganming Qin, Moaniss Zitouni
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Patent number: 11489072Abstract: A MOSFET includes a substrate having a body region of a first conductivity type. A main field effect transistor (mainFET) and a mirror device are formed in the substrate. The mainFET includes first gate trenches, first source regions of a second conductivity type adjacent to the first gate trenches, and first body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the first source regions. The mirror device includes second gate trenches, second source regions of the second conductivity type adjacent to the second gate trenches, second body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the second source regions, and link elements of the first conductivity type interconnecting pairs of the second body implant regions.Type: GrantFiled: April 7, 2021Date of Patent: November 1, 2022Assignee: NXP USA, Inc.Inventors: Ganming Qin, Feng Li, Vishnu Khemka, Moaniss Zitouni, Tanuj Saxena
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Publication number: 20220231161Abstract: A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Tanuj Saxena, Vishnu Khemka, Bernhard Grote, Ganming Qin, Moaniss Zitouni
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Patent number: 11329150Abstract: A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.Type: GrantFiled: April 14, 2020Date of Patent: May 10, 2022Assignee: NXP USA, Inc.Inventors: Tanuj Saxena, Vishnu Khemka, Bernhard Grote, Ganming Qin, Moaniss Zitouni
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Publication number: 20210320200Abstract: A semiconductor device includes a substrate having opposed first and second major surface, an active area, and a termination area. Insulated trenches extend from the first major surface toward the second major surface, each of the insulated trenches including a conductive field plate and a gate electrode overlying the conductive field plate, the gate electrode being separated from the field plate by a gate-field plate insulator. The field plate extends longitudinally in both of the active and termination areas and the gate electrode is absent in the termination area. A body region of a first conductivity type extends laterally between pairs of the insulated trenches. First and second spacer regions of a second conductivity type extend laterally between the pairs of the insulated trenches at the termination area to produce segments of the first conductivity type between the first and second spacer regions that are isolated from the body region.Type: ApplicationFiled: April 14, 2020Publication date: October 14, 2021Inventors: Tanuj Saxena, Vishnu Khemka, Bernhard Grote, Ganming Qin, Moaniss Zitouni
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Publication number: 20210226054Abstract: A MOSFET includes a substrate having a body region of a first conductivity type. A main field effect transistor (mainFET) and a mirror device are formed in the substrate. The mainFET includes first gate trenches, first source regions of a second conductivity type adjacent to the first gate trenches, and first body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the first source regions. The mirror device includes second gate trenches, second source regions of the second conductivity type adjacent to the second gate trenches, second body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the second source regions, and link elements of the first conductivity type interconnecting pairs of the second body implant regions.Type: ApplicationFiled: April 7, 2021Publication date: July 22, 2021Inventors: Ganming Qin, Feng Li, Vishnu Khemka, Moaniss Zitouni, Tanuj Saxena
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Patent number: 11004970Abstract: A MOSFET includes a substrate having a body region of a first conductivity type. A main field effect transistor (mainFET) and a mirror device are formed in the substrate. The mainFET includes first gate trenches, first source regions of a second conductivity type adjacent to the first gate trenches, and first body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the first source regions. The mirror device includes second gate trenches, second source regions of the second conductivity type adjacent to the second gate trenches, second body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the second source regions, and link elements of the first conductivity type interconnecting pairs of the second body implant regions.Type: GrantFiled: May 20, 2019Date of Patent: May 11, 2021Assignee: NXP USA, Inc.Inventors: Ganming Qin, Feng Li, Vishnu Khemka, Moaniss Zitouni, Tanuj Saxena
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Publication number: 20200373426Abstract: A MOSFET includes a substrate having a body region of a first conductivity type. A main field effect transistor (mainFET) and a mirror device are formed in the substrate. The mainFET includes first gate trenches, first source regions of a second conductivity type adjacent to the first gate trenches, and first body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the first source regions. The mirror device includes second gate trenches, second source regions of the second conductivity type adjacent to the second gate trenches, second body implant regions of the first conductivity type extending into the body region adjacent to and interposed between the second source regions, and link elements of the first conductivity type interconnecting pairs of the second body implant regions.Type: ApplicationFiled: May 20, 2019Publication date: November 26, 2020Inventors: Ganming Qin, Feng Li, Vishnu Khemka, Moaniss Zitouni, Tanuj Saxena
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Patent number: 10811502Abstract: A method for manufacturing a super-junction MOSFET entails forming a recessed shield electrode in a trench in a semiconductor layer of a substrate, the trench being lined with a first oxide layer. When the electrically conductive material forming the shield electrode is removed to recess the shield electrode, the first oxide layer on sidewalls of the trench is exposed. Removal of the first oxide layer from the sidewalls and from shield sidewalls of the electrode produces openings at a top part of the shield sidewalls. A second oxide layer is formed over the shield electrode and fills the openings. Part of the second oxide layer is removed to expose a top surface of the shield electrode. A gate dielectric is formed over the top surface of the shield electrode and conductive material is deposited over the gate dielectric in the trench to form a gate electrode of the MOSFET.Type: GrantFiled: May 30, 2019Date of Patent: October 20, 2020Assignee: NXP USA, Inc.Inventors: Vishnu Khemka, Tanuj Saxena, Ganming Qin, Raghuveer Vankayala Gupta, Mark Edward Gibson, Moaniss Zitouni
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Patent number: 10672902Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.Type: GrantFiled: April 8, 2019Date of Patent: June 2, 2020Assignee: NXP USA, Inc.Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin
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Publication number: 20200152786Abstract: A vertical bi-directional device includes first and second conductive gates in a semiconductor layer with a first vertical gate oxide on a sidewall of the first conductive gate and a second vertical gate oxide on a sidewall of the second conductive gate. A first heavily doped region of a first conductivity type is at the surface adjacent the first conductive gate, and a second heavily doped region of the first conductive type is at the surface adjacent to the second conductive gate. Doped regions of the first conductivity type extend below the conductive gates towards a substrate. A doped region of a second conductivity type extends laterally from the first vertical gate oxide to the second vertical gate oxide, and a heavily doped region of the second conductivity type is at the surface of the semiconductor layer, between the first and second heavily doped regions of the first conductivity type.Type: ApplicationFiled: November 13, 2018Publication date: May 14, 2020Inventors: Moaniss ZITOUNI, Vishnu KHEMKA, Ganming QIN, Tanuj SAXENA, Raghuveer Vankayala GUPTA, Mark Edward GIBSON
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Patent number: 10644146Abstract: A vertical bi-directional device includes first and second conductive gates in a semiconductor layer with a first vertical gate oxide on a sidewall of the first conductive gate and a second vertical gate oxide on a sidewall of the second conductive gate. A first heavily doped region of a first conductivity type is at the surface adjacent the first conductive gate, and a second heavily doped region of the first conductive type is at the surface adjacent to the second conductive gate. Doped regions of the first conductivity type extend below the conductive gates towards a substrate. A doped region of a second conductivity type extends laterally from the first vertical gate oxide to the second vertical gate oxide, and a heavily doped region of the second conductivity type is at the surface of the semiconductor layer, between the first and second heavily doped regions of the first conductivity type.Type: GrantFiled: November 13, 2018Date of Patent: May 5, 2020Assignee: NXP USA, Inc.Inventors: Moaniss Zitouni, Vishnu Khemka, Ganming Qin, Tanuj Saxena, Raghuveer Vankayala Gupta, Mark Edward Gibson
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Patent number: 10607880Abstract: A continuous buried doped isolation region in a substrate of a die. The substrate includes an isolation ring structure surrounding a first area of the die. The continuous buried doped isolation region is of a net first conductivity type and is located in the first area. The continuous buried doped isolation region including a first portion having a net first conductivity type dopant concentration of at least a first level located in an interior region of the first area and extending to a sidewall of the isolation ring structure. The first portion does not extend to the sidewall of the isolation ring structure in a location of a corner area of the first area. The corner area is defined by the isolation ring structure. A second portion of the continuous buried doped isolation region in the corner area has a net first conductivity type dopant concentration of a second level that is lower than the first level.Type: GrantFiled: August 30, 2018Date of Patent: March 31, 2020Assignee: NXP USA, INC.Inventors: Saumitra Raj Mehrotra, Tanuj Saxena, Ljubo Radic, Bernhard Grote
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Publication number: 20200075393Abstract: A continuous buried doped isolation region in a substrate of a die. The substrate includes an isolation ring structure surrounding a first area of the die. The continuous buried doped isolation region is of a net first conductivity type and is located in the first area. The continuous buried doped isolation region including a first portion having a net first conductivity type dopant concentration of at least a first level located in an interior region of the first area and extending to a sidewall of the isolation ring structure. The first portion does not extend to the sidewall of the isolation ring structure in a location of a corner area of the first area. The corner area is defined by the isolation ring structure. A second portion of the continuous buried doped isolation region in the corner area has a net first conductivity type dopant concentration of a second level that is lower than the first level.Type: ApplicationFiled: August 30, 2018Publication date: March 5, 2020Inventors: Saumitra Raj Mehrotra, Tanuj Saxena, Ljubo Radic, Bernhard Grote
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Patent number: 10431678Abstract: A plurality of trench stripes are disposed in parallel in an epitaxial layer on a drain and extends from a top region to a bottom region of a first surface of the semiconductor. A first polysilicon layer is in each of the trench stripes. The first polysilicon layer extends between the drain and the first surface proximal to the top region and the bottom region, and between the drain and a level below the first surface in a middle region between the top region and the bottom region. A second polysilicon layer is over the first polysilicon layer in the middle region, wherein the first poly silicon layer forms a shield, and the second polysilicon layer forms a gate. A source is in a silicon mesa stripe surrounding the first trench stripe.Type: GrantFiled: July 18, 2018Date of Patent: October 1, 2019Assignee: NXP USA, Inc.Inventors: Ganming Qin, Vishnu Khemka, Ljubo Radic, Bernhard Grote, Tanuj Saxena, Moaniss Zitouni
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Publication number: 20190237571Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin
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Patent number: 10323980Abstract: A sensor system, device and method for generating a wireless signal in response to a sensed illumination. A sensor is disclosed having: a photosensitive element; a device that converts a sensed illumination detected by the photosensitive element into a corresponding impedance response; and a wireless signal generator that generates a wireless output based on a characteristic of the corresponding impedance response, wherein the wireless output correlates to the sensed illumination.Type: GrantFiled: March 28, 2014Date of Patent: June 18, 2019Assignee: Rensselaer Polytechnic InstituteInventors: Tanuj Saxena, Partha Sarathi Dutta, Serguei Lvovich Roumiantsev, Michael Shur
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Patent number: 10297684Abstract: A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET.Type: GrantFiled: September 29, 2017Date of Patent: May 21, 2019Assignee: NXP USA, Inc.Inventors: Tanuj Saxena, Vishnu K. Khemka, Raghu Gupta, Moaniss Zitouni, Ganming Qin