Patents by Inventor Tanveer R Khondker

Tanveer R Khondker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dyanamically adapting a voltage of a clock generation circuit
    Patent number: 9965019
    Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 8, 2018
    Assignee: Intel Corporation
    Inventors: Tapan A. Ganpule, Inder M. Sodhi, Yair Talker, Inbar Falkov, Tanveer R. Khondker
  • DYANAMICALLY ADAPTING A VOLTAGE OF A CLOCK GENERATION CIRCUIT
    Publication number: 20160370839
    Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Tapan A. Ganpule, Inder M. Sodhi, Yair Talker, Inbar Falkov, Tanveer R. Khondker
  • Dyanamically adapting a voltage of a clock generation circuit
    Patent number: 9459689
    Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Tapan A. Ganpule, Inder M. Sodhi, Yair Talker, Inbar Falkov, Tanveer R. Khondker
  • DYANAMICALLY ADAPTING A VOLTAGE OF A CLOCK GENERATION CIRCUIT
    Publication number: 20150177824
    Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 25, 2015
    Inventors: Tapan A. Ganpule, Inder M. Sodhi, Yair Talker, Inbar Falkov, Tanveer R. Khondker
  • Method and apparatus for testing an integrated device's input/output (I/O)
    Patent number: 7496803
    Abstract: A plurality of timing diagrams and different versions of circuits to test an integrated device in a test mode of operation. The invention allows for pulling in a strobe and eliminating the need for delay cells in strobe pads and a clock generation that facilitates varying the duty cycle for pulling in the strobe and pushing out the data.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: February 24, 2009
    Assignee: Intel Corporation
    Inventors: Tanveer R. Khondker, Matthew B. Nazareth, Vijay K. Vuppaladadium
  • Selecting a first clock signal based on a comparison between a selected first clock signal and a second clock signal
    Patent number: 7043654
    Abstract: According to some embodiments, a potential clock signal is selected based on a comparison between a selected first clock signal and a second clock signal.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Tanveer R. Khondker, Mathew B. Nazareth
  • Circuits and methods for alignment of signals in integrated circuits
    Patent number: 6891417
    Abstract: Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on at least one of the phase lock loop signals. The alignment unit aligns internal signal with the external signal based on the code.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: May 10, 2005
    Assignee: Intel Corporation
    Inventors: Tanveer R Khondker, Vijay Vuppaladadium, Inder Sodhi, Venkatesh Prasanna, Kedar Mangrulkar, Miguel Corvacho, Nakul Arora
  • Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states
    Publication number: 20040255176
    Abstract: A method and apparatus automatically transferring to an enhanced low-power state of a processor is disclosed. In one embodiment, either all or a portion of a processor core clock distribution grid may be powered down in these enhanced low-power states. In one embodiment, the processor may operate in a reduced power supply voltage and operate at a reduced frequency during these enhanced low-power states. In one embodiment, a portion of the clock distribution grid may be left on to support snoop operations at a reduced frequency.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 16, 2004
    Inventors: Varghese George, Mark A. Newman, Sanjeev Jahagirdar, Inder M. Sodhi, Tanveer R. Khondker, Mathew B. Nazareth, John B. Conrad
  • Selecting a first clock signal based on a comparison between a selected first clock signal and a second clock signal
    Publication number: 20040128579
    Abstract: According to some embodiments, a potential clock signal is selected based on a comparison between a selected first clock signal and a second clock signal.
    Type: Application
    Filed: December 31, 2002
    Publication date: July 1, 2004
    Inventors: Tanveer R. Khondker, Mathew B. Nazareth