Abstract: An SRAM cell includes a first active region, a first gate structure, a second gate structure, and a first source/drain contact region. The first gate structure is over the first active region and forms a pull-up transistor with the first active region. The second gate structure is over the first active region and forms a write-assist transistor with the first active region. The write-assist transistor and the pull-up transistor are of a same conductivity type. The first source/drain contact region is over a source/drain of the write-assist transistor and a source/drain of the pull-up transistor.

Abstract: A method includes forming a first pull-up transistor and a first pass-gate transistor over a substrate at a first level height, the first pull-up and first pass-gate transistors being of a dual port static random access memory (SRAM) cell; forming a first pull-down transistor and a second pass-gate transistor of the dual port SRAM cell over the substrate at a second level height; forming a second pull-down transistor and a third pass-gate transistor of the dual port SRAM cell over the substrate at a third level height; forming a second pull-up transistor and a fourth pass-gate transistor of the dual port SRAM cell over the substrate at a fourth level height.

Abstract: A memory device includes a memory array, a first reference voltage circuit, a first read voltage control circuit and a first write voltage control circuit. The first reference voltage circuit is configured to provide a first reference voltage signal having a first voltage level to the memory array. The first read voltage control circuit is configured to adjust the first reference voltage signal to a second voltage level when the memory array is read. The first write voltage control circuit is configured to adjust the first reference voltage signal to a third voltage level when the memory array is written. The second voltage level is higher than the first voltage level, and the third voltage level is lower than the first voltage level.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: A memory device includes a first pull-down transistor, a first pass-gate transistor, a second pull-down transistor, a second pass-gate transistor, a first pull-up transistor, and a second pull-up transistor. A first power line, a first bit line, and a second bit line is provided, the first power line includes first and second portions separated from each other, wherein in a cross-sectional view, the second portion of the first power line is laterally between the first and second bit lines along a direction. A first via electrically connects the first portion of the first power line to the first pull-down transistor. A second via electrically connects the first bit line to the first pass-gate transistor. A third via electrically connects the second portion of the first power line to the second pull-down transistor. A fourth via electrically connects the second bit line to the second pass-gate transistor.

Abstract: A method includes forming a sacrificial multi-layer stack including first, second, and third sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layer to form a first space; depositing a first dielectric layer and a first electrode material in the first space; removing the second sacrificial layer to form a second space; depositing a second dielectric layer and a second electrode material in the second space; removing the third sacrificial layer to form a third space; depositing a third dielectric layer and a third electrode material in the third space.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A semiconductor structure includes a ceramic substrate, a first bonding layer, a second bonding layer, a cavity, and a semiconductor layer. The ceramic substrate includes holes on its surface. The first bonding layer is disposed on the surface of the ceramic substrate, and the second bonding layer is bonded to the first bonding layer. The cavity is disposed above the hole and enclosed by the first bonding layer and the second bonding layer. The semiconductor layer extends over the cavity and is disposed along the surface of the second bonding layer.

Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.

Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.

Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.

Abstract: A computer mouse with vibration function includes a base, a press control module disposed on a front portion of the base, a palm support disposed on a rear portion of the base, a vibrator installed on the palm support for receiving the signal from the computer, and a plurality of vibration damping units each of which includes a vibration damper abutting between the palm support and the base. The vibration dampers of the vibration damping units are disposed around the vibrator.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate and a seed layer on the substrate. The substrate includes a base and a composite layer encapsulating the base. The semiconductor structure also includes an epitaxial layer on the seed layer. The semiconductor structure also includes a semiconductor device on the epitaxial layer, and an interlayer dielectric layer on the epitaxial layer. The interlayer dielectric layer covers the semiconductor device. The semiconductor structure further includes a via structure that penetrates at least the composite layer of the substrate and is in contact with the base.

Abstract: A smart wheel is provided, including a main body, at least one wheel body and a GPS module. The main body includes a pin and a wheel seat, and the wheel seat is connected with the pin. The at least one wheel body is pivoted to the wheel seat along an axial direction. The GPS module is arranged on the main body and includes a GPS chip.

Abstract: A substrate structure and a method for fabricating a semiconductor structure including the substrate structure are provided. The substrate structure includes a substrate, a bow adjustment layer, and a silicon layer. The bow adjustment layer is on the top surface of the substrate. The silicon layer is on the bow adjustment layer. The substrate structure has a total bow value, and the total vow value is from ?20 ?m to ?40 ?m.

Abstract: A semiconductor structure, a high electron mobility transistor (HEMT), and a method for fabricating a semiconductor structure are provided. The semiconductor structure includes a substrate, a flowable dielectric material pad layer, a reflow protection layer, and a GaN-based semiconductor layer. The substrate has a pit exposed from a top surface of the substrate. The flowable dielectric material pad layer is formed in the pit, and a top surface of the flowable dielectric material pad layer is below the top surface of the substrate. The reflow protection layer is formed on the substrate and the top surface of the flowable dielectric material pad layer. The GaN-based semiconductor layer is disposed over the substrate.

Abstract: A smart wheel is provided, including a main body, at least one wheel body and a GPS module. The main body includes a pin and a wheel seat, and the wheel seat is connected with the pin. The at least one wheel body is pivoted to the wheel seat along an axial direction. The GPS module is arranged on the main body and includes a GPS chip.