Abstract: A network task offload apparatus includes an offload circuit and a buffer scheduler. The offload circuit performs corresponding network task processing on a plurality of packets in parallel according to an offload command. The buffer scheduler includes a buffer control unit and a plurality of buffer units. The plurality of buffer units are controlled by the buffer control unit and are scheduled to store the processed packets.

Abstract: A data transmission circuit applied to a universal serial bus (USB) system includes a memory, a direct memory access (DMA) engine and a USB controller. The memory is arranged for receiving and storing external data. The DMA engine is coupled to the memory, and arranged for controlling data retrieved from the memory. The USB controller is coupled to the DMA engine, and arranged for receiving data from the DMA engine and for transmitting the received data to a host. When the memory the stored data volume reaches a first threshold, the DMA engine starts continuously fetching data from the memory and transmitting it to the USB controller, until the data volume fetched by the DMA engine reaches a second threshold, or there is no data left in the memory. The second threshold is greater than the first threshold.

Abstract: A data transmission circuit applied to a universal serial bus (USB) system includes a memory, a direct memory access (DMA) engine and a USB controller. The memory is arranged for receiving and storing external data. The DMA engine is coupled to the memory, and arranged for controlling data retrieved from the memory. The USB controller is coupled to the DMA engine, and arranged for receiving data from the DMA engine and for transmitting the received data to a host. When the memory the stored data volume reaches a first threshold, the DMA engine starts continuously fetching data from the memory and transmitting it to the USB controller, until the data volume fetched by the DMA engine reaches a second threshold, or there is no data left in the memory. The second threshold is greater than the first threshold.

Abstract: A network task offload apparatus includes an offload circuit and a buffer scheduler. The offload circuit performs corresponding network task processing on a plurality of packets in parallel according to an offload command. The buffer scheduler includes a buffer control unit and a plurality of buffer units. The plurality of buffer units are controlled by the buffer control unit and are scheduled to store the processed packets.