Abstract: A multi-timescale voltage regulation method based on source-grid-load-storage multi -terminal collaboration of a power distribution network is disclosed, which comprises: establishing, based on a Petri network, a multi-mode switching control model based on voltage security event trigger to realize effective control of a global voltage; establishing multi-objective optimization taking into account a source-storage-load regulation cost and a network transmission loss to realize collaborative and dynamic control of controllable resources of a source terminal, a load terminal and a storage terminal in each operating mode; and establishing a source-storage-load multi-terminal collaboration-based distributed voltage control model based on voltage security event trigger over a short timescale by taking into account the problems of voltage magnitude being out of limit and voltage leap, and solving online an optimal control sequence of the source terminal, the load terminal and the storage terminal in a receding horiz

Abstract: Disclosed are an emergency control method and system based on source-load-storage regulation and cutback. According to the method, output power of power generating sources is regulated according to a power regulating quantity and a frequency regulation requirement, an output power compensation and output frequency of each power generating source are maintained within permissible ranges, so that a balance between power supply and demand of a power distribution network is maintained; and standby energy-storage power stations are used to make up a power gap, and an external power supply system is used to assist in making up a power deficiency, so that large load disturbance can be handled make up the power gap.

Abstract: A semiconductor device includes a substrate including a memory region and a peripheral region located at an outer side of the memory region; a memory structure located above the memory region and including a memory array and signal lines, the memory array at least including memory cells spaced apart from each other along a first direction, and the signal lines being electrically connected with the memory cells, the first direction is perpendicular to the top surface of the substrate; a peripheral structure located above the peripheral region and including peripheral stacked layers, peripheral circuits located above the peripheral stacked layer, and peripheral leads located above the peripheral circuits, one end of each peripheral lead being electrically connected with at least one of peripheral circuits, and the other end being electrically connected with at least one of signal lines.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes providing a to-be-etched layer; forming an initial mask layer over the to-be-etched layer; forming a patterned structure, on the initial mask layer and exposing a portion of the initial mask layer; forming a barrier layer on a sidewall surface of the patterned structure; using the patterned structure and the barrier layer as a mask, performing an ion doping process on the initial mask layer to form a doped region and an un-doped region between doped regions in the initial mask layer; removing the patterned structure and the barrier layer; and forming a mask layer on a top surface of the to-be-etched layer by removing the un-doped region. The mask layer includes a first opening exposing the top surface of the to-be-etched layer.

Abstract: A method of forming a semiconductor structure includes providing a to-be-etched layer, forming a core layer over the to-be-etched layer, the core layer including a first trench extending along a first direction, forming a sidewall spacer layer on a top surface of the core layer and on sidewalls and a bottom surface of the first trench, forming a block cut structure in the first trench after forming the sidewall spacer layer, and after forming the block cut structure, etching back the sidewall spacer layer until exposing the top surface of the core layer, thereby leaving a sidewall spacer on the sidewalls of the first trench. The block cut structure extends through the first trench along a second direction. The second direction and the first direction are different. The block cut structure includes a first block-cut layer and a second block-cut layer.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes providing a to-be-etched layer; forming an initial mask layer over the to-be-etched layer; forming a patterned structure, on the initial mask layer and exposing a portion of the initial mask layer; forming a barrier layer on a sidewall surface of the patterned structure; using the patterned structure and the barrier layer as a mask, performing an ion doping process on the initial mask layer to form a doped region and an un-doped region between doped regions in the initial mask layer; removing the patterned structure and the barrier layer; and forming a mask layer on a top surface of the to-be-etched layer by removing the un-doped region. The mask layer includes a first opening exposing the top surface of the to-be-etched layer.

Abstract: A method of forming a semiconductor structure includes providing a to-be-etched layer, forming a core layer over the to-be-etched layer, the core layer including a first trench extending along a first direction, forming a sidewall spacer layer on a top surface of the core layer and on sidewalls and a bottom surface of the first trench, forming a block cut structure in the first trench after forming the sidewall spacer layer, and after forming the block cut structure, etching back the sidewall spacer layer until exposing the top surface of the core layer, thereby leaving a sidewall spacer on the sidewalls of the first trench. The block cut structure extends through the first trench along a second direction. The second direction and the first direction are different. The block cut structure includes a first block-cut layer and a second block-cut layer.