Abstract: A wireless direct contact charger includes (a) a voltage supply; (b) a first plate electrode and a second plate electrode; (c) a polarity detection circuit that detects; and (d) a switching circuit. When the first electrode or the second electrode of the portable device is placed on the first plate electrode or the second plate electrode, the polarity detection circuit detects the polarity of the portable device charging terminals (i.e, whether the first electrode of the portable device is in contact with the first plate electrode, the second electrode of the portable device is in contact with the first plate electrode or any other suitable orientations). Based on the detected polarity, the switching circuit connects the first plate electrode and the second plate electrode to the voltage supply to provide an output voltage to the portable device for charging its battery.

Abstract: A wireless charger and a method allow the wireless charger to have enhanced portability and a smaller footprint when not performing the charging function. The wireless charger includes a charging circuit providing power on one or more power lines, a housing for the wireless charger, and a flexible platform that includes a charging surface with two or more contact electrodes. The flexible platform may be unfolded or unrolled for charging a mobile device, and folded up or rolled up to achieve a smaller footprint, when not performing a charging operation. The wireless charger may further includes a data communication circuit for data communication between a power-line network and the mobile device.

Abstract: The present invention provides for EMI mitigation in switching circuitry, such as power converters, by implementing a controlled, non-random change in frequency in every cycle of switch control signals based on a static or dynamically changing modulation cycle. This permits frequency spreading across a wide range while avoiding excessive jitter between cycles and voltage dropouts common to randomized EMI control circuitry. Further, since it may be implemented digitally, some embodiments may avoid performance, size and power consumption problems experienced by mixed signal or analog switch control circuitry and EMI control circuitry. Further still, implementations of the present invention may mitigate EMI from a constant frequency source without the necessity of a variable frequency source, such as one generated by a VCO, to realize frequency variation.

Abstract: The present disclosure provides a display method and an electronic device. The method comprises: obtaining a third display content based on the first display content when the first electronic device is to be controlled by the second electronic device; and transmitting the third display content to the second electronic device to cause the second electronic device to display a fourth display content based on the third display content, the fourth display content being different from the first display content.

Abstract: A charging system for a mobile device includes a transmitter and a receiver. The transmitter includes (a) a first interface to a power source; (b) a second interface to the receiver; (c) a polarity detection circuit for detecting polarities of the; and (d) first and second switches controlled by the polarity detection circuit, wherein each switch selectively connects a terminal of the first interface to a terminal of the second interface. The receiver includes: (a) a first interface; (b) a second interface coupled to a device to be charged; and (c) a connection circuit between a terminal of the first interface and a terminal of the second interface, wherein the connection circuit is conductive when the voltage across these terminals is of a first polarity, and a second polarity otherwise.

Abstract: A computer and a method for controlling an operating state of a device thereof are disclosed. The method comprises: detecting that a display portion and a host portion of the computer are in a state of being disconnected from each other; and generating a state event or a control instruction corresponding to the disconnected state for switching the device to an inactive state. With the present invention, when the state of a computer changes, e.g., when a display portion and a host portion of a portable computer are separated, an operating system can control a device to switch its operating state, e.g., deactivate the device, based on a generated state event. In this way, it is possible to avoid unnecessary power consumption of the entire computer due to the active state of the device, and any potential security risk can be eliminated.

Abstract: A method and apparatus for implementation of high order MASH by reuse of single stage MASH have been described.

Abstract: A wireless direct contact charger includes (a) a voltage supply; (b) a first plate electrode and a second plate electrode; (c) a polarity detection circuit that detects; and (d) a switching circuit. When the first electrode or the second electrode of the portable device is placed on the first plate electrode or the second plate electrode, the polarity detection circuit detects the polarity of the portable device charging terminals (i.e, whether the first electrode of the portable device is in contact with the first plate electrode, the second electrode of the portable device is in contact with the first plate electrode or any other suitable orientations).

Abstract: The present invention provides a method of establishing a hard disk physical partition. First of all, it selects a sector in which the head of the hard disk physical partition is located, and establishes a user available partition of the hard disk within the range of the hard disk physical volume from the sector, the other portion of the hard disk becomes a protected partition of the hard disk, finally constitutes one hard disk physical partition. After entering into the hard disk physical partition, only the user available partition can be accessed, the protected partition is invisible to the user. It can establish the different hard disk physical partition in the different position of the hard disk through selecting the sector where the head of the hard disk is located.

Abstract: A system status control method and a portable terminal are described. The portable terminal includes a first system with a first interface and a second system with a second interface, and the first system and the second system are joined or separated through the first interface and the second interface. The method includes when the first system and the second system enter a joined-up status from a separated status, the first system and the second system exchanging respective system status information thereof; and the first system and the second system control the system status according to the system status information and based on a preset policy. When a master system and a slave system are combined or separated, automatic switch control may be performed on the system status according to a usage requirement of a user and based on the preset policy.

Abstract: An apparatus includes an adjustable oscillator circuit configured to generate an output signal having a frequency that varies responsive to a frequency control signal and a frequency reference generator circuit configured to produce a frequency reference signal. The apparatus further includes a calibration circuit configured to determine a relationship of the output signal to the frequency reference signal and to enable and disable the frequency reference generator circuit based on the determined relationship.

Abstract: The present invention provides a file synchronization method, an electronic device and a synchronization system. The method comprises: in a hybrid system having a first system and a second system, monitoring in the first system a first cache of the first system, in which first data corresponding to a first file stored in a non-volatile storage of the first system opened by a first file processing program of the first system is saved; sending, to the second system, operating content performed by the first file processing program on the first file via a data information channel between the first system and the second system, when the first data in the first cache is changed; wherein a second file processing program in the second system performs a synchronization processing on a second file according to the operating content, the second file being a file corresponding to the first file in the second system.

Abstract: A computer and a method for controlling an operating state of a device thereof are disclosed. The method comprises: detecting that a display portion and a host portion of the computer are in a state of being disconnected from each other; and generating a state event or a control instruction corresponding to the disconnected state for switching the device to an inactive state. With the present invention, when the state of a computer changes, e.g., when a display portion and a host portion of a portable computer are separated, an operating system can control a device to switch its operating state, e.g., deactivate the device, based on a generated state event. In this way, it is possible to avoid unnecessary power consumption of the entire computer due to the active state of the device, and any potential security risk can be eliminated.

Abstract: The present invention provides for EMI mitigation in switching circuitry, such as power converters, by implementing a controlled, non-random change in frequency in every cycle of switch control signals based on a static or dynamically changing modulation cycle. This permits frequency spreading across a wide range while avoiding excessive jitter between cycles and voltage dropouts common to randomized EMI control circuitry. Further, since it may be implemented digitally, some embodiments may avoid performance, size and power consumption problems experienced by mixed signal or analog switch control circuitry and EMI control circuitry. Further still, implementations of the present invention may mitigate EMI from a constant frequency source without the necessity of a variable frequency source, such as one generated by a VCO, to realize frequency variation.

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.

Abstract: An electrostatic discharge (ESD) protection circuit configured completely inside one of a power pad and an I/O pad of an electronic circuit, the ESD protection circuit comprising an electrostatic discharge (ESD) circuit that, when activated, discharges an ESD from a first voltage bus to a second voltage bus. The second voltage bus is at a lower electrical potential than the first voltage bus. An ESD discharge control circuit in electrical connection with the ESD discharge circuit that controls the activation of the ESD discharge circuit and including an NMOS transistor and an electrical node. The NMOS transistor regulating a rate of voltage decay of the electrical node from a predetermined high voltage level to a lower voltage level, the regulation of the rate of voltage decay of the electrical node is non-linear. The activation of the ESD discharge circuit determined by the rate of voltage decay of the electrical node.

Abstract: A clock circuit includes a phase-lock loop for generating an output clock signal based on a data signal and a harmonic frequency detector for detecting whether the frequency of the output clock signal is a harmonic frequency of a frequency of a reference clock signal. The harmonic frequency detector includes a counter for generating a first divided clock signal by dividing the frequency of the output clock signal by a first divisor. Additionally, the harmonic frequency detector includes a counter for generating a second divided clock signal by dividing the frequency of the reference clock signal by a second divisor. The harmonic frequency detector also includes a frequency comparator for generating an output indicating whether the frequency of the output clock signal is a harmonic frequency of the frequency of the reference clock signal based on the first divided clock signal and the second divided clock signal.

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.

Abstract: An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.