Abstract: A method and system is presented for measuring a data access time of an embedded macro module in an integrated circuit. A single external test signal is inputted into the embedded macro module for enabling a data input therein and extracting a data output therefrom. A pulse width of the single external test signal is incrementally increased until a latch of the data output is observed. Then, the data access time is obtained, as its substantially equals a time interval of the increased pulse width.

Abstract: A method and system is presented for measuring a data access time of an embedded macro module in an integrated circuit. A single external test signal is inputted into the embedded macro module for enabling a data input therein and extracting a data output therefrom. A pulse width of the single external test signal is incrementally increased until a latch of the data output is observed. Then, the data access time is obtained, as its substantially equals a time interval of the increased pulse width.

Abstract: A device to control a sense amplifier comprise a resetable control circuit containing a first input, a second input, a third input, and an output; the first input coupled to the output or to a ground; the second input coupled to receive a start signal; the third input coupled to receive output signals of the sense amplifier; the output coupled to the sense amplifier.

Abstract: A yield enhancement circuit substitutes a redundant sub-circuit for a faulty sub-circuit in an integrated circuit such as memory. The yield enhancement circuit has a plurality of fault indication devices, which is associated with one sub circuit of the integrated circuits such that one fault indication device is activated to generate a fault signal to express the existence of a fault within the faulty sub-circuit. Additionally selected adjacent fault indication devices generate the fault signal to express the existence of the fault within the faulty circuit. A fault detection device determines the existence of the faulty sub-circuit and transmits a redundancy implementation signal to a plurality of redundancy activation circuits. Each redundancy activation circuit selectively transfers input/output signals to a designated path dependent on the expression of the existence of a fault within the integrated circuit.

Abstract: A yield enhancement circuit substitutes a redundant sub-circuit for a faulty sub-circuit in an integrated circuit such as memory. The yield enhancement circuit has a plurality of fault indication devices, which is associated with one sub circuit of the integrated circuits such that one fault indication device is activated to generate a fault signal to express the existence of a fault within the faulty sub-circuit. Additionally selected adjacent fault indication devices generate the fault signal to express the existence of the fault within the faulty circuit. A fault detection device determines the existence of the faulty sub-circuit and transmits a redundancy implementation signal to a plurality of redundancy activation circuits. Each redundancy activation circuit selectively transfers input/output signals to a designated path dependent on the expression of the existence of a fault within the integrated circuit.

Abstract: A device to control a sense amplifier comprise a resetable control circuit containing a first input, a second input, a third input, and an output; the first input coupled to the output or to a ground; the second input coupled to receive a start signal; the third input coupled to receive output signals of the sense amplifier; the output coupled to the sense amplifier.

Abstract: A reset circuit in a memory device applies a reset to the global X-address latch and the local X-address latch. This resets those latches and effectively de-addresses all word lines prior to application of the next address. This eliminates any overlap of main word line signals between successive addresses thereby eliminating a possible glitch that would cause simultaneous word line addressing and potentially a memory read or write error. By terminating the addressing, the address cycle time may be reduced.