Abstract: A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.

Abstract: A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.