Patents by Inventor Tao Yi HUNG

Tao Yi HUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220139903
    Abstract: A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Tao-Yi HUNG, Wun-Jie LIN, Jam-Wem LEE, Kuo-Ji CHEN, Chia-En HUANG
  • Publication number: 20210366846
    Abstract: A semiconductor device includes a device wafer having a first side and a second side. The first and second sides are opposite to each other. The semiconductor device includes a plurality of first interconnect structures disposed on the first side of the device wafer. The semiconductor device includes a plurality of second interconnect structures disposed on the second side of the device wafer. The plurality of interconnect structures comprise a first power rail and a second power rail. The semiconductor device includes a carrier wafer disposed over the plurality of first interconnect structures. The semiconductor device includes an electrostatic discharge (ESD) protection circuit formed over a side of the carrier wafer. The ESD protection circuit is operatively coupled to the first and second power rails.
    Type: Application
    Filed: March 26, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Tao Yi Hung, Jam-Wem Lee, Kuo-Ji Chen, Wun-Jie Lin
  • Publication number: 20210305809
    Abstract: A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node. The clamp circuit further includes a first transistor of a first type. The first transistor has a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. The clamp circuit further includes a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node.
    Type: Application
    Filed: December 1, 2020
    Publication date: September 30, 2021
    Inventors: Tao Yi HUNG, Ming-Fang LAI, Li-Wei CHU, Wun-Jie LIN, Jam-Wem LEE