Abstract: The precharge circuit includes circuitry for initiating charging of a precharge pulse at a first edge of a first clock-like signal. The precharge circuit also includes circuitry for ending the charging of the precharge pulse after a time period that is longer of a preset delay period and a time period designated by a second edge of the second clock-like signal.

Abstract: A precharge circuit capable of generating a precharge pulse is provided. The precharge circuit includes circuitry for initiating charging of a precharge pulse at a first edge of a first clock-like signal. The precharge circuit also includes circuitry for ending the charging of the precharge pulse after a time period that is longer of a preset delay period and a time period designated by a second edge of the second clock-like signal. Methods for generating a precharge pulse are also included.

Abstract: A system for minimizing the effect of clock skew in a precharge circuit includes a switch coupled between an input to the precharge circuit and a global bitline; and a control circuit coupled to a precharge component and the switch. The control circuit determines whether the switch and the precharge component are activated and the control circuit receives feedback from the switch. A method of minimizing the effect of clock skew in a precharge circuit includes controlling whether an input signal outputting a first signal and a second signal from the precharge circuit; controlling the outputting of the second signal from the precharge circuit based on a clock signal, a select signal, and a dynamic signal.

Abstract: A system for minimizing the effect of clock skew in a bit line write driver includes a first control circuit coupled to the bit line write driver; and a second control circuit coupled to the bit line write driver. The bit line write driver outputs a first output signal and a second output signal. A method of minimizing the effect of clock skew in a bit line write driver includes outputting a first signal and a second signal from the bit line write driver; controlling the outputting of the second signal from the bit line write driver based on a feedback of the first signal; and controlling the outputting of the first signal from the bit line write driver based on feedback of the second signal.

Abstract: A system for minimizing the effect of clock skew in a bit line write driver includes a first control circuit coupled to the bit line write driver; and a second control circuit coupled to the bit line write driver. The bit line write driver outputs a first output signal and a second output signal. The first control circuit receives feedback from the second output signal and controls whether the bit line write driver outputs the first output signal based on the feedback from the second output signal and the second control circuit receives feedback from the first output signal and controls whether the bit line write driver outputs the second output signal based on the feedback from the first output signal.