Patents by Inventor Tao Yu Chen

Tao Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240119283
    Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Jui-Yang Hsu, Cheng-Sheng Chan, Jen-Chieh Tsai, Huai-Ting Li, Bo-Yu Kuo, Yen-Hao Chen, Kai-Ling Huang, Ping-Yuan Tseng, Tao Tu, Sheng-Je Hung
  • Patent number: 11932637
    Abstract: The present invention relates to monobactam compounds of Formula I: and pharmaceutically acceptable salts thereof. The present invention also relates to compositions which comprise a monobactam compound of structural formula I or a pharmaceutically acceptable salt thereof, and a pharmaceutically acceptable carrier. The invention further relates to methods for treating a bacterial infection comprising administering to the patient a therapeutically effective amount of a compound of structural formula I, either alone or in combination with a therapeutically effective amount of a second beta-lactam antibiotic.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: March 19, 2024
    Assignee: Merck Sharp & Dohme LLC
    Inventors: Helen Y. Chen, Shuzhi Dong, Zhiyong Hu, Jing Su, Tao Yu, Yong Zhang
  • Patent number: 7168352
    Abstract: A process for sawing a substrate strip marks corresponding to substrate areas of substrate strips which are arranged side-by-side on a plate. A saw machine is mechanically moved to the substrate areas and positioned by the alignment marks of corresponding substrate areas for cutting the substrate areas of the substrate strips in the first phase. Then the saw machine is further mechanically moved to the substrate areas again and is positioned by the alignment marks of corresponding substrate areas again for cutting the substrate areas of the substrate strips in the second phase. Therefore, an error in any of the substrate areas in the first phase and second phase will not accumulate to the subsequent substrate areas in the substrate strip.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: January 30, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Jau-Yuen Su, Tao-Yu Chen, Su Tao
  • Patent number: 6338813
    Abstract: A molding method for a BGA semiconductor chip package comprising a substrate supporting an array of chips having two lines of bonding pads formed at two respective side thereof. The molding method comprises the steps of: (A) providing a molding apparatus comprising a molding die having a molding cavity and at least two runners connected to the molding cavity; (B) closing and clamping the molding die in a manner that the chips are located in the molding cavity thereof; (C) transferring a molding compound into the molding cavity wherein each chip is arranged in a manner that the two lines of bonding pads thereof are substantially perpendicular to the flowing direction of the molding compound; (D) curing the molding compound; and (E) unclamping and opening the molding die to take out the molded product.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: January 15, 2002
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kao-Yu Hsu, Chun Hung Lin, Tao-Yu Chen
  • Publication number: 20010048999
    Abstract: A flexible substrate includes a substrate constructed in a form of a tape, the substrate including patterns formed on at least one of an upper side and a bottom side thereof. The tape includes sprocket holes defied in each of two lateral edges thereof. A supporting layer is applied to at least one of the upper side and the bottom side of the substrate at an area not covered by the patterns to reinforce the substrate.
    Type: Application
    Filed: March 19, 1998
    Publication date: December 6, 2001
    Inventors: CHEN KUN-CHING, TAO-YU CHEN, YUNG-I YEH, CHUN-CHE LEE
  • Patent number: 6316828
    Abstract: The structure of a solder mask for the circuit module of a BGA substrate mainly comprises a power ring, a ground ring, a plurality of holes, a plurality of first holes and a plurality of second holes. The power ring and the ground ring are arranged between the chip area and the wire bonding area; the first openings are arranged on the power ring and the ground ring for receiving the electronic part. Thus the substrate meets the requirement of keeping the electronic part close to the chip. The second openings are arranged over the associated holes which electrically connect to the power ring and the ground ring by traces; these holes do need not to electrically connect the power layer and the ground layer of the substrate. The openings of the present invention use the power ring, ground ring and the holes of the substrate to electrically connect to the electronic parts, so that the present invention does not need to provide other holes or traces thus simplifying the structure of the substrate.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: November 13, 2001
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Su Tao, Tao-Yu Chen, Kao-Yu Hsu
  • Patent number: 6176417
    Abstract: A ball bonding method on a chip mainly comprises steps of: a wire is burned to form a ball on a capillary; the capillary is moved down to a second bonding point for ball bonding; and the capillary is moved up in a vertical direction thereby pulling the tip of the ball to be cut such that the ball has a uniformly body shape and tip height. Therefore, the ball provides uniform body shape and tip height for wire bonding at a second bonding point under lower variability conditions thus increasing the reliability of products.
    Type: Grant
    Filed: October 15, 1999
    Date of Patent: January 23, 2001
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Yu-Fang Tsai, Su Tao, Simon Lee, Tao Yu Chen
  • Patent number: 5982625
    Abstract: A semiconductor packaging device includes a printed circuit board substrate, a mold gate formed on a periphery of the printed circuit board substrate through which a package encapsulant is poured to enclose electric elements mounted on a side of the printed circuit board, and a layer of non-metallic material covered on the side of the printed circuit board substrate in the mold gate area. The package encapsulant, after hardened, is bonded with the layer of non-metallic material, and the bonded package encapsulant/the layer of non-metallic material is degatable from the mold gate.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: November 9, 1999
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kun-Ching Chen, Tao-Yu Chen, Yung-I Yeh, Wu-Chang Wang, Chun-Che Lee, Chun-Hsiung Huang, Shyh-Ing Wu