Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a programming operation, programming a plurality of threshold voltages of a plurality of switches on a plurality of string select lines and a plurality of ground select lines as a first reference threshold voltage, and programming a plurality of threshold voltages of a plurality of dummy memory cells on a plurality of dummy word lines as being gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells being higher than the first reference threshold voltage; wherein the first direction being from the string select lines to a plurality of word lines and the second direction being from the ground select lines to the word lines.

Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a programming operation, programming a plurality of threshold voltages of a plurality of switches on a plurality of string select lines and a plurality of ground select lines as a first reference threshold voltage, and programming a plurality of threshold voltages of a plurality of dummy memory cells on a plurality of dummy word lines as being gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells being higher than the first reference threshold voltage; wherein the first direction being from the string select lines to a plurality of word lines and the second direction being from the ground select lines to the word lines.

Abstract: A method for operating a memory array is provided. The memory array comprises a first NAND memory string comprising a ith memory cell, a i?1th memory cell, a ith word line, and a i?1th word line. The ith memory cell and the i?1th memory cell are arranged in a sequent order with a series electrical connection. The ith word line is electrically connected to the ith memory cell. The i?1th word line is electrically connected to the i?1th memory cell. The method for operating the memory array comprises in an operating time interval, performing a program inhibiting process to the ith memory cell, and simultaneously performing a first process to the ith memory cell. The program inhibiting process comprises providing a first pre-turn on voltage to the ith word line. The first process comprises providing a second pre-turn on voltage to the i?1th word line.

Abstract: A method for performing a program inhibit operation with cell disturbance alleviation, a memory device and a controller are provided. The method includes the following steps. A verify operation is performed on a cell string of a cell array. A power pulse is applied on the cell string. The program inhibit operation is performed on the cell string. The step of applying the power pulse is performed before the step of performing the program inhibit operation.

Abstract: A memory device includes N word lines, wherein the word lines include an ith word line coupled to an ith memory cell and an (i+1)th word line coupled to an (i+1)th memory cell which is disposed adjacent to the ith memory cell and is a programmed memory cell, and i is an integer from 0 to (N?2). A method of operating such a memory device method includes a reading step. In the reading step, a read voltage is provided to the ith word line, a first pass voltage is provided to the (i+1)th word line, and a second pass voltage is provided to the others of the word lines, wherein the second pass voltage is lower than the first pass voltage.

Abstract: A method for forming a semiconductor device includes forming a gate structure over a substrate, performing a lightly-doped drain (LDD) implantation of first dopant ions into the substrate using the gate structure as a mask to form LDD regions in the substrate, performing, after the LDD implantation, a pre-amorphization implantation (PAI) into the substrate using the gate structure as a mask to pre-amorphize at least a portion of the LDD regions, and performing, after the PAI, a high-doping implantation of second dopant ions into the substrate using the gate structure as a mask to form highly-doped regions at least partially overlapping the LDD regions.

Abstract: A non-volatile memory structure includes a source and a drain. The memory structure includes a substrate and a dielectric layer on the substrate. The memory structure further has a gate, which can be a floating gate, on the dielectric layer. A recess is on the drain side and nearest to the bottom corner of the dielectric layer. The recess is configured to reduce the electric field density around the bottom corner nearest to the drain in order to reduce the damage on the dielectric layer when the memory is under a bias.

Abstract: The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.

Abstract: The memory device is described, which includes a substrate, a conductive layer, a plurality of charge storage layers and a plurality of doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layers are disposed between the substrate and the conductive layer in the trenches respectively, wherein the charge storage layers are separated from each other. The doped regions are configured in the substrate under bottoms of the trenches, respectively.