Abstract: In some aspects, the present disclosure provides a method for testing an integrated circuit (IC). In some configurations, the method includes determining, by a test controller embedded in the IC, a change in operation of the IC from a normal mode to a test mode. The method also includes communicating, by the test controller to a chain of data storage elements in the IC: a first test signal configured to change an input/output (I/O) function of a first IC pin, and a second test signal configured to apply one of a plurality of test functions to each data storage element in the chain of data storage elements. The method also includes, receiving, via a second IC pin, a test clock signal configured to control a latch function of each data storage element in the chain of data storage elements.

Abstract: In some aspects, the present disclosure provides a method for testing an integrated circuit (IC). In some configurations, the method includes determining, by a test controller embedded in the IC, a change in operation of the IC from a normal mode to a test mode. The method also includes communicating, by the test controller to a chain of data storage elements in the IC: a first test signal configured to change an input/output (I/O) function of a first IC pin, and a second test signal configured to apply one of a plurality of test functions to each data storage element in the chain of data storage elements. The method also includes, receiving, via a second IC pin, a test clock signal configured to control a latch function of each data storage element in the chain of data storage elements.

Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.

Abstract: An integrated circuit (IC) is disclosed herein for embedded memory testing with storage borrowing. In an example aspect, an integrated circuit includes a functional logic block, a memory block, and test logic. The functional logic block includes multiple storage units and is configured to store functional data in the multiple storage units during a regular operational mode. The test logic is configured to perform a test on the memory block during a testing mode. The test logic is also configured to retain memory test result data in the multiple storage units of the functional logic block during the testing mode.

Abstract: Test architectures for multi-die chips are provided herein according to embodiments of the present disclosure. In certain aspects, an exemplary test architecture enables an external tester to perform various tests on a multi-die chip that includes multiple dies. In a first test mode, the test architecture enables the external tester to currently perform die-level tests on the multiple dies. In a second test mode, the test architecture enables the external tester to perform a chip-level test on the multi-die chip. The chip-level test may include die-to-die tests for testing interconnections between the multiple dies on the multi-die chip. The chip-level test may also include a boundary input/output (I/O) test for testing external connections between the multi-die chip and one or more devices external to the multi-die chip.

Abstract: An integrated circuit (IC) is disclosed herein for embedded memory testing with storage borrowing. In an example aspect, an integrated circuit includes a functional logic block, a memory block, and test logic. The functional logic block includes multiple storage units and is configured to store functional data in the multiple storage units during a regular operational mode. The test logic is configured to perform a test on the memory block during a testing mode. The test logic is also configured to retain memory test result data in the multiple storage units of the functional logic block during the testing mode.

Abstract: The invention includes a method and apparatus for injecting dynamic faults in a circuit device. The apparatus includes a first register adapted with selection data identifying selected ones of a plurality of outputs of the circuit device and/or selected ones of a plurality of error registers of the circuit device, a second register adapted with dynamic fault data for propagation toward the selected ones of the outputs of the circuit device and/or the selected ones of the error registers of the circuit device, and a controller for applying the selection data to the first register and the dynamic fault data to the second register in a manner for providing a dynamic fault on each of the selected ones of the outputs of the circuit device and/or each of the selected ones of the error registers of the circuit device.

Abstract: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.

Abstract: A register designed to detect and correct soft errors in real time. A redundant latch is added to the existing structure of a flip flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voting circuit. If the content of any of these latches is corrupted by soft error, it is filtered out through the majority voting circuit and correct data is passed out from the output of the flip flop. In one embodiment, this design operates as a simple scan flip flop or scan-hold flip flop, and is useful for system testability purposes.

Abstract: The invention includes a method and apparatus for injecting dynamic faults in a circuit device. The apparatus includes a first register adapted with selection data identifying selected ones of a plurality of outputs of the circuit device and/or selected ones of a plurality of error registers of the circuit device, a second register adapted with dynamic fault data for propagation toward the selected ones of the outputs of the circuit device and/or the selected ones of the error registers of the circuit device, and a controller for applying the selection data to the first register and the dynamic fault data to the second register in a manner for providing a dynamic fault on each of the selected ones of the outputs of the circuit device and/or each of the selected ones of the error registers of the circuit device.

Abstract: A method and system for testing circuit clusters in a boundary scan environment identifies the circuit clusters and corresponding neighboring boundary scan elements, and generates one or more test vectors to be applied to the cluster under test. The generated test vectors are serialized and input into an identified boundary scan element connected to the cluster being tested in the form of a boundary scan test chain. The output of the applied test vectors is observed from an output of another correspondingly identified boundary scan element connected to the cluster under test. During generation of test vectors a list of faults for detecting by each generated vector is maintained such that the observed output can be used to diagnose faults at the component level within the identified cluster.

Abstract: Testing time of interconnections is reducted by splitting up the collection of connection paths to be tested into two or more groups. A set of test vectors, which is applied to each of the groups concurrently, is arranged to insure that the two adjacent connections that are assigned to different groups are not tested concurrently. The user can select the number of groups, and the number of connection paths within each group (which need not be the same for all groups). The disclosed algorithm increases the number of connection paths that are tested with each concatenated test vector, and consequently the number of required test vectors is reduced.

Abstract: A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion and a plurality of scan flip-flops. The BIST structure includes a test pattern generator for generating two test patterns and a controller for generating a clock signal and an extended scan mode signal which is held high for two clock cycles while the output response of the combinational portion to the first and second test vectors is latched into the scan flip-flops in order to detect a signal transition. The invention is further directed to a method for detection of path-delay faults using this scan-based BIST architecture. To improve the fault coverage for path-delay faults, observation points may be inserted at the inputs of selected scan flip-flops. A predetermined number of scan flip-flops having the highest activation frequency are selected as the observation points.

Abstract: Apparatus and method for testing the components and interconnections of a circuit board while the circuit board is, normally, operatively connected in a system. The circuit board contains a plurality of integrated circuits with at least one of the integrated circuits including interface circuitry for interfacing the circuitry on the circuit board to the rest of the system. The circuit board includes testing circuitry for: (a) selectively testing the circuits contained on the circuit board, other than its interface circuits; and (b) selectively testing the interface circuits and their interconnections. The method of the invention includes placing the interface circuitry in a first state for isolating the circuitry on the circuit board from the rest of the system and testing the circuitry on the circuit board, other than the interface circuitry; and placing the interface circuitry in a second state and testing the interface circuitry and its interconnections.