Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer.

Abstract: Hardware optimization of neural networks is provided. In various embodiments, an output-induced receptive field of each of a plurality of layers of a neural network is determined. From each of the plurality of layers any portions of their respective input that falls outside their respective output-induced receptive field are trimmed. For each of the plurality of layers, a plurality of mappings of the layer to physical neurosynaptic cores are determined. A mapping is determined having a minimum total number of cores required for the neural network based on the plurality of mappings.

Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, the neural inference chip is adapted to: receive an input activation tensor comprising a plurality of input activations; receive a weight tensor comprising a plurality of weights; Booth recode each of the plurality of weights into a plurality of Booth-coded weights, each Booth coded value having an order; multiply the input activation tensor by the Booth coded weights, yielding a plurality of results for each input activation, each of the plurality of results corresponding to the orders of the Booth-coded weights; for each order of the Booth-coded weights, sum the corresponding results, yielding a plurality of partial sums, one for each order; and compute a neural activation from a sum of the plurality of partial sums.

Abstract: Hardware placement of neural networks is provided. In various embodiments, a network description is read. The network description describes a spiking neural network. The neural network is trained. An initial placement of the neural network on a plurality of cores is performed. The cores are located on a plurality of chips. Inter-chip communications are measured based on the initial placement. A final placement of the neural network on the plurality of cores is performed based on the inter-chip communications measurements and the initial placement. The final placement reduces inter-chip communication.

Abstract: Graph partitioning and placement for multi-chip neurosynaptic networks. According to various embodiments, a neural network description is read. The neural network description describes a plurality of neurons. The plurality of neurons has a mapping from an input domain of the neural network. The plurality of neurons is labeled based on the mapping from the input domain. The plurality of neurons is grouped into a plurality of groups according to the labeling. Each of the plurality of groups is continuous within the input domain. Each of the plurality of groups is assigned to at least one neurosynaptic core.

Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer.

Abstract: Detection, tracking and recognition on networks of digital neurosynaptic cores are provided. In various embodiments, an image sensor is configured to provide a time-series of frames. A first artificial neural network is operatively coupled to the image sensor and configured to detect a plurality of objects in the time-series of frames. A second artificial neural network is operatively coupled to the first artificial neural network and configured to classify objects detected by the first neural network and output a location and classification of said classified objects. The first and second artificial neural networks comprise one or more spike-based neurosynaptic cores.

Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, the neural inference chip is adapted to: receive an input activation tensor comprising a plurality of input activations; receive a weight tensor comprising a plurality of weights; Booth recode each of the plurality of weights into a plurality of Booth-coded weights, each Booth coded value having an order; multiply the input activation tensor by the Booth coded weights, yielding a plurality of results for each input activation, each of the plurality of results corresponding to the orders of the Booth-coded weights; for each order of the Booth-coded weights, sum the corresponding results, yielding a plurality of partial sums, one for each order; and compute a neural activation from a sum of the plurality of partial sums.

Abstract: Detection, tracking and recognition on networks of digital neurosynaptic cores are provided. In various embodiments, an image sensor is configured to provide a time-series of frames. A first artificial neural network is operatively coupled to the image sensor and configured to detect a plurality of objects in the time-series of frames. A second artificial neural network is operatively coupled to the first artificial neural network and configured to classify objects detected by the first neural network and output a location and classification of said classified objects. The first and second artificial neural networks comprise one or more spike-based neurosynaptic cores.

Abstract: Hardware optimization of neural networks is provided. In various embodiments, an output-induced receptive field of each of a plurality of layers of a neural network is determined. From each of the plurality of layers any portions of their respective input that falls outside their respective output-induced receptive field are trimmed. For each of the plurality of layers, a plurality of mappings of the layer to physical neurosynaptic cores are determined. A mapping is determined having a minimum total number of cores required for the neural network based on the plurality of mappings.

Abstract: Applications in a data center can be consolidated by identifying different combinations of software executing on hardware. The software can include a set of applications that execute upon a set of servers. The different combinations can have different arrangements of applications running on different ones of the servers. For each of the different combinations, a licensing cost, an operating cost, and a total cost can be calculated. The total cost of operation for each of the configurations can be calculated by summing the licensing costs, the operating costs adjusted for the cost savings for complementary workload patterns, and migration costs for adjusting a current configuration of the applications and servers to arrive at the configuration. The total cost results per configuration can be reported to a user for at least a set of the configurations.

Abstract: Neurosynaptic systems for computing characteristics of a set are provided. In various embodiments, a plurality of encoders is provided. Each encoder is adapted to receive a population coded input and generate an encoded output. The encoded output comprises a plurality of segments. Each segment corresponds to one or more binary bits. A winner selection component is adapted to receive the encoded outputs from the plurality of encoders and to perform a method comprising: proceeding from highest order to lowest order of the segments of the encoded outputs of the encoders, performing a bitwise OR operation across all segments of equivalent order; disqualifying each encoded output whose bits do not match the result of the bitwise OR operation across all segments of equivalent order; outputting remaining encoded outputs.

Abstract: Hardware placement of neural networks is provided. In various embodiments, a network description is read. The network description describes a spiking neural network. The neural network is trained. An initial placement of the neural network on a plurality of cores is performed. The cores are located on a plurality of chips. Inter-chip communications are measured based on the initial placement. A final placement of the neural network on the plurality of cores is performed based on the inter-chip communications measurements and the initial placement. The final placement reduces inter-chip communication.

Abstract: Methods, systems, and computer program products for structured representation and classification of noisy and unstructured tickets are provided herein.

Abstract: Graph partitioning and placement for multi-chip neurosynaptic networks. According to various embodiments, a neural network description is read. The neural network description describes a plurality of neurons. The plurality of neurons has a mapping from an input domain of the neural network. The plurality of neurons is labeled based on the mapping from the input domain. The plurality of neurons is grouped into a plurality of groups according to the labeling. Each of the plurality of groups is continuous within the input domain. Each of the plurality of groups is assigned to at least one neurosynaptic core.

Abstract: Methods, systems, and computer program products for analyzing tickets using discourse cues in communication logs are provided herein. A computer-implemented method includes analyzing a plurality of communication logs associated with a query related to an information technology issue to determine one or more discourse relationships between the plurality of communication logs; generating a hierarchical structure representing the plurality of communication logs and the one or more determined discourse relationships; associating the query with one or more classified queries by (i) determining one or more patterns in the hierarchical structure and (ii) comparing the one or more determined patterns to patterns associated with multiple historical hierarchical structures associated with classified queries; and determining one or more information technology issue categories applicable to the query based on said associating.

Abstract: Methods, systems, and computer program products for analyzing tickets using discourse cues in communication logs are provided herein. A computer-implemented method includes analyzing a plurality of communication logs associated with a query related to an information technology issue to determine one or more discourse relationships between the plurality of communication logs; generating a hierarchical structure representing the plurality of communication logs and the one or more determined discourse relationships; associating the query with one or more classified queries by (i) determining one or more patterns in the hierarchical structure and (ii) comparing the one or more determined patterns to patterns associated with multiple historical hierarchical structures associated with classified queries; and determining one or more information technology issue categories applicable to the query based on said associating.

Abstract: Methods, systems, and computer program products for structured representation and classification of noisy and unstructured tickets are provided herein.

Abstract: Methods and systems for creating an action plan for a service delivery system comprising a plurality of operational key performance indicators (KPIs). The system receives predetermined information about at least one relationship between two or more of the KPIs, and weights that information based on its source. The system also receives information about operational constraints and desired outcomes. A KPI relationship map is created using both the weighted information and information about KPI relationships within the service delivery system. Future predictions are made based on the KPI relationship map, and the predictions and map are utilized to create an action plan to achieve the desired outcomes in light of the operational constraints.

Abstract: Techniques for virtual machine placement in a datacenter are provided. The techniques include using one or more server power characteristics to determine a power cost for any given virtual machine placement in the datacenter, using a heat profile of one or more datacenter components in relation to one or more cooling resources in the datacenter to determine cooling cost for any given virtual machine placement in the datacenter, and using the power cost and cooling cost to apply integrated energy cost minimization at one or more levels of hierarchy in the datacenter to determine placement of a virtual machine in the datacenter such that the integrated energy cost of the datacenter is minimized.