Abstract: This document describes low-latency Bluetooth connectivity in a wireless network in which a central node and a peripheral node establish a connection. During a first connection interval, the peripheral node receives a packet from the central node to synchronize communication with the central node, and based on receiving the packet, the peripheral node transmits a first fixed-length packet. If the first fixed-length packet fails to reach the central node, the peripheral node does not receive an acknowledgement, ACK, from the central node during the first connection interval and retransmits the first fixed-length packet during the first connection interval.

Abstract: This document describes low-latency Bluetooth connectivity in a wireless network in which a central node and a peripheral node establish a connection. During a first connection interval, the peripheral node receives a packet from the central node to synchronize communication with the central node, and based on receiving the packet, the peripheral node transmits a first fixed-length packet. If the first fixed-length packet fails to reach the central node, the peripheral node does not receive an acknowledgement, ACK, from the central node during the first connection interval and retransmits the first fixed-length packet during the first connection interval.

Abstract: A reduced oxide stress cascode stack circuit includes a cascade transistor stack and dynamic bias circuits that supply an output voltage having a magnitude greater than an oxide reliability voltage of their component transistors. The reduced oxide stress cascode stack circuit also includes an offset voltage generator that provides an offset voltage based on a transient extreme of the output voltage, wherein the offset voltage is applied to the cascade transistor stack and the dynamic bias circuits to reduce component transistor voltages commensurate with the oxide reliability voltage. The reduced oxide stress cascode stack circuit further includes a bias voltage supply that modifies a bias voltage value of the cascade transistor stack and dynamic bias circuits by an amount proportional to the offset voltage. A method of reducing oxide stress in a cascode stack circuit is also provided.

Abstract: A system, method, and computer program product are provided for performing level shifting. In use, level shifting is performed utilizing a native transistor, where the level shifting is performed utilizing a feedback based topology.

Abstract: A system, method, and computer program product are provided for performing level shifting. In use, level shifting is performed utilizing a native transistor, where the level shifting is performed utilizing a feedback based topology.

Abstract: The present invention significantly reduces the chip size of a metal-oxide-semiconductor (MOS) field-effect transistor, which serves as a driver for output impedance drivers, such as, but not limited to, double data rate (DDR2) synchronous dynamic random access memory (SDRAM). In an embodiment of the invention, a voltage drop across the driver is a decreased ratio of the supply voltage, e.g., three-tenths of the supply voltage, lower than half of the supply voltage. A smaller voltage drop allows a lower current and a higher impedance to be used in the driver. By having a higher impedance across the driver, the physical area needed for the DDR2 driver is reduced because a transistor with a smaller physical width can be used. A DDR2 driver operating at the decreased ratio is the functional equivalent of the driver operating with the supply voltage or half of the supply voltage, with the added advantage of the reduced area.