Patents by Inventor Tapash Chakraborty

Tapash Chakraborty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170207361
    Abstract: An improved method of doping a workpiece is disclosed. The method is particularly beneficial to the creation of interdigitated back contact (IBC) solar cells. A patterned implant is performed on one surface of the workpiece. A self-aligned masking process is then performed, which is achieved by exploiting the changes in surface properties caused by the patterned implant. The masking process includes applying a coating that preferentially adheres to the previously implanted regions. A blanket implant is then performed, which serves to implant the portions of the workpiece that are not covered by the coating. Thus, the blanket implant is actually a complementary implant, doping the regions that were not implanted by the first patterned implant. The coating is then optionally removed from the workpiece.
    Type: Application
    Filed: January 14, 2016
    Publication date: July 20, 2017
    Inventors: Vikram M. Bhosle, Timothy J. Miller, Tapash Chakraborty, Prerna Goradia, Robert J. Visser
  • Publication number: 20170092533
    Abstract: Methods of selectively depositing a patterned layer on exposed dielectric material but not on exposed metal surfaces are described. A self-assembled monolayer (SAM) is deposited using phosphonic acids. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the exposed metal portion and the tail moiety extending away from the patterned substrate and reducing the deposition rate of the patterned layer above the exposed metal portion relative to the deposition rate of the patterned layer above the exposed dielectric portion. A dielectric layer is subsequently deposited by atomic layer deposition (ALD) which cannot initiate in regions covered with the SAM in embodiments.
    Type: Application
    Filed: December 2, 2015
    Publication date: March 30, 2017
    Inventors: Tapash Chakraborty, Mark Saly, Rana Howlader, Eswaranand Venkatasubramanian, Prerna Sonthalia Goradia, Robert Jan Visser, David Thompson
  • Publication number: 20160247994
    Abstract: Single source precursors, methods to synthesize single source precursors and methods to deposit nanowire based thin films using single source precursors for high efficiency thermoelectric devices are provided herein. In some embodiments, a method of forming a single source precursor includes mixing a first compound with one of SbX3, SbX5, Sb2(SO4)3 or with one of BiX3, Bi(NO3)3, Bi(OTf)3, Bi(PO4), Bi(OAc)3, wherein the first compound is one of a lithium selenolate, a lithium tellurolate, a monoselenide, or a monotelluride.
    Type: Application
    Filed: September 11, 2015
    Publication date: August 25, 2016
    Inventors: Ranga Rao ARNEPALLI, Tapash CHAKRABORTY, Robert Jan VISSER
  • Publication number: 20160172238
    Abstract: A method of forming features in a low-k dielectric layer is described. A via, trench or a dual damascene structure may be present in the low-k dielectric layer prior to depositing a conformal hermetic layer. The conformal hermetic layer is configured to keep water and contaminants out. Some of the same conformal hermetic layer may deposit on the underlying copper. The portion of the conformal hermetic layer on the underlying copper is preferentially removed but the beneficial portion on the low-k dielectric layer remains. The selective removal of the conformal hermetic layer may be accomplished using a dry etch or a wet etch using a weak organic acid.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Bhaskar Kumar, Deenesh Padhi, Alexandros T. Demos, Tapash Chakraborty, Geetika Bajaj, Robert Jan Visser
  • Patent number: 9257330
    Abstract: Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: February 9, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Amit Chatterjee, Geetika Bajaj, Pramit Manna, He Ren, Tapash Chakraborty, Srinivas D. Nemani, Mehul Naik, Robert Jan visser, Abhijit Basu Mallick
  • Publication number: 20150147879
    Abstract: Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.
    Type: Application
    Filed: September 11, 2014
    Publication date: May 28, 2015
    Inventors: Amit Chatterjee, Geetika Bajaj, Pramit Manna, He Ren, Tapash Chakraborty, Srinivas D. Nemani, Mehul Naik, Robert Jan visser, Abhijit Basu Mallick